module artix_pcie(
    input  wire             sys_clk_p,
    input  wire             sys_clk_n,

    input  wire             rst_n,

    input  wire             pcie_exp_clkp,
    input  wire             pcie_exp_clkn,

    output wire [1 : 0]     pci_exp_txp,
    output wire [1 : 0]     pci_exp_txn,
    input  wire [1 : 0]     pci_exp_rxp,
    input  wire [1 : 0]     pci_exp_rxn,

    output wire [3:0]       led
);

logic pcie_refclk;

logic axis_clk;
logic axis_rst;

logic link_up;
logic app_ready;

assign led[0] = ~link_up;
assign led[1] = ~app_ready;

logic [63:0]    axis_tdata;
logic [7:0]     axis_tkeep;
logic           axis_tlast;
logic           axis_tvalid;
logic           axis_tready;
logic [21:0]    axis_tuser;



IBUFDS_GTE2 #(
    .CLKRCV_TRST("TRUE"),
    .CLKCM_CFG("TRUE"),
    .CLKSWING_CFG(2'b11)
) pcie_ibuf (
    .I      (pcie_exp_clkp),
    .IB     (pcie_exp_clkn),
    .CEB    ('0),
    .O      (pcie_refclk),
    .ODIV2  ()
);

pcie_7x_0 u_pcie_7x_0 (
    .pci_exp_txp            (pci_exp_txp),
    .pci_exp_txn            (pci_exp_txn),
    .pci_exp_rxp            (pci_exp_rxp),
    .pci_exp_rxn            (pci_exp_rxn),

    .user_clk_out           (axis_clk),
    .user_reset_out         (axis_rst),
    .user_lnk_up            (link_up),
    .user_app_rdy           (app_ready),

    .s_axis_tx_tready       (),
    .s_axis_tx_tdata        ('0),
    .s_axis_tx_tkeep        ('0),
    .s_axis_tx_tlast        ('0),
    .s_axis_tx_tvalid       ('0),
    .s_axis_tx_tuser        ('0),
    
    .m_axis_rx_tdata        (axis_tdata),
    .m_axis_rx_tkeep        (axis_tkeep),
    .m_axis_rx_tlast        (axis_tlast),
    .m_axis_rx_tvalid       (axis_tvalid),
    .m_axis_rx_tready       (axis_tready),
    .m_axis_rx_tuser        (axis_tuser),

    .cfg_interrupt          ('0),
    .cfg_interrupt_rdy      (),
    .cfg_interrupt_assert   ('0),
    .cfg_interrupt_di       ('0),
    .cfg_interrupt_do       (),
    .cfg_interrupt_mmenable (),
    .cfg_interrupt_msienable(),
    .cfg_interrupt_msixenable(),
    .cfg_interrupt_msixfm   (),
    .cfg_interrupt_stat     ('0),
    .cfg_pciecap_interrupt_msgnum('0),

    .sys_clk                (pcie_refclk),
    .sys_rst_n              (rst_n),
    
    .pcie_drp_clk           ('0),
    .pcie_drp_en            ('0),
    .pcie_drp_we            ('0),
    .pcie_drp_addr          ('0),
    .pcie_drp_di            ('0),
    .pcie_drp_do            (),
    .pcie_drp_rdy           ()
);

assign axis_tready = '1;

ila_0 u_ila_0 (
    .clk                    (axis_clk),

    .probe0                 (axis_tready),
    .probe1                 (axis_tdata),
    .probe2                 (axis_tstrb),
    .probe3                 (axis_tvalid),
    .probe4                 (axis_tlast),
    .probe5                 (axis_tuser),
    .probe6                 (axis_tkeep),
    .probe7                 ('0),
    .probe8                 ('0)
);

endmodule