116 lines
2.9 KiB
Systemverilog
116 lines
2.9 KiB
Systemverilog
module artix_pcie(
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input wire sys_clk_p,
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input wire sys_clk_n,
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input wire rst_n,
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input wire pcie_exp_clkp,
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input wire pcie_exp_clkn,
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output wire [1 : 0] pci_exp_txp,
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output wire [1 : 0] pci_exp_txn,
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input wire [1 : 0] pci_exp_rxp,
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input wire [1 : 0] pci_exp_rxn,
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output wire [3:0] led
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);
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logic pcie_refclk;
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logic axis_clk;
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logic axis_rst;
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logic link_up;
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logic app_ready;
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assign led[0] = ~link_up;
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assign led[1] = ~app_ready;
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logic [63:0] axis_tdata;
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logic [7:0] axis_tkeep;
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logic axis_tlast;
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logic axis_tvalid;
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logic axis_tready;
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logic [21:0] axis_tuser;
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IBUFDS_GTE2 #(
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.CLKRCV_TRST("TRUE"),
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.CLKCM_CFG("TRUE"),
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.CLKSWING_CFG(2'b11)
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) pcie_ibuf (
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.I (pcie_exp_clkp),
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.IB (pcie_exp_clkn),
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.CEB ('0),
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.O (pcie_refclk),
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.ODIV2 ()
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);
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pcie_7x_0 u_pcie_7x_0 (
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.pci_exp_txp (pci_exp_txp),
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.pci_exp_txn (pci_exp_txn),
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.pci_exp_rxp (pci_exp_rxp),
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.pci_exp_rxn (pci_exp_rxn),
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.user_clk_out (axis_clk),
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.user_reset_out (axis_rst),
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.user_lnk_up (link_up),
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.user_app_rdy (app_ready),
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.s_axis_tx_tready (),
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.s_axis_tx_tdata ('0),
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.s_axis_tx_tkeep ('0),
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.s_axis_tx_tlast ('0),
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.s_axis_tx_tvalid ('0),
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.s_axis_tx_tuser ('0),
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.m_axis_rx_tdata (axis_tdata),
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.m_axis_rx_tkeep (axis_tkeep),
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.m_axis_rx_tlast (axis_tlast),
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.m_axis_rx_tvalid (axis_tvalid),
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.m_axis_rx_tready (axis_tready),
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.m_axis_rx_tuser (axis_tuser),
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.cfg_interrupt ('0),
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.cfg_interrupt_rdy (),
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.cfg_interrupt_assert ('0),
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.cfg_interrupt_di ('0),
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.cfg_interrupt_do (),
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.cfg_interrupt_mmenable (),
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.cfg_interrupt_msienable(),
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.cfg_interrupt_msixenable(),
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.cfg_interrupt_msixfm (),
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.cfg_interrupt_stat ('0),
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.cfg_pciecap_interrupt_msgnum('0),
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.sys_clk (pcie_refclk),
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.sys_rst_n (rst_n),
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.pcie_drp_clk ('0),
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.pcie_drp_en ('0),
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.pcie_drp_we ('0),
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.pcie_drp_addr ('0),
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.pcie_drp_di ('0),
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.pcie_drp_do (),
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.pcie_drp_rdy ()
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);
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assign axis_tready = '1;
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ila_0 u_ila_0 (
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.clk (axis_clk),
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.probe0 (axis_tready),
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.probe1 (axis_tdata),
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.probe2 (axis_tstrb),
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.probe3 (axis_tvalid),
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.probe4 (axis_tlast),
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.probe5 (axis_tuser),
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.probe6 (axis_tkeep),
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.probe7 ('0),
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.probe8 ('0)
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);
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endmodule
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