diff --git a/src/build_fpga/build_fpga.py b/src/build_fpga/build_fpga.py
index 73a0d0f..55217fd 100644
--- a/src/build_fpga/build_fpga.py
+++ b/src/build_fpga/build_fpga.py
@@ -7,12 +7,13 @@ from rtl_manifest import rtl_manifest
 import yaml
 
 from .efinity import efinity
+from .vivado import vivado
 
 def build_fpga_main():
 
     parser = argparse.ArgumentParser(
-        prog="sim",
-        description="Tool to simulate"
+        prog="build_fpga",
+        description="Tool to automate building fpga images"
     )
 
     parser.add_argument("yaml")
@@ -24,4 +25,6 @@ def build_fpga_main():
 
     if (cfg["tool"] == "efinity"):
         efinity.create_project(cfg)
+    elif (cfg["tool"] == "vivado"):
+        vivado.build_nonprj(cfg)
 
diff --git a/src/build_fpga/vivado/__init__.py b/src/build_fpga/vivado/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/src/build_fpga/vivado/vivado.py b/src/build_fpga/vivado/vivado.py
new file mode 100644
index 0000000..61b449a
--- /dev/null
+++ b/src/build_fpga/vivado/vivado.py
@@ -0,0 +1,42 @@
+import rtl_manifest
+import os
+
+def build_nonprj(cfg):
+    all_sources = rtl_manifest.read_sources(cfg["design_info"]["sources"])
+
+    verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv")), all_sources))
+    xci_sources = list(filter(lambda s: s.endswith(".xci"), all_sources))
+    xdc_sources = list(filter(lambda s: s.endswith(".xdc"), all_sources))
+
+    top = cfg["design_info"]["top_module"]
+    part = cfg["device_info"]["device"]
+
+    with open("build.tcl", "w") as f:
+        f.write(f"set outputDir ./nonprojectflow\n")
+        f.write(f"file mkdir $outputDir\n")
+
+        f.write(f"set_part {part}\n")
+
+        f.write(f"read_verilog {' '.join(verilog_sources)}\n")
+        f.write(f"read_ip {' '.join(xci_sources)}\n")
+        f.write(f"read_xdc {' '.join(xdc_sources)}\n")
+        
+        f.write(f"synth_ip [get_ips *]\n")
+        f.write(f"synth_design -top {top}\n")
+        f.write(f"write_checkpoint -force $outputDir/post_synth.dcp\n")
+        f.write(f"report_utilization -file $outputDir/post_synth_util.rpt\n")
+
+        f.write(f"opt_design\n")
+        f.write(f"place_design\n")
+        f.write(f"write_checkpoint -force $outputDir/post_place.dcp\n")
+        f.write(f"route_design\n")
+        f.write(f"write_checkpoint -force $outputDir/post_route.dcp\n")
+        f.write(f"report_utilization -file $outputDir/post_impl_util.rpt\n")
+        f.write(f"write_bitstream -force $outputDir/{top}.bit\n")
+        f.write(f"exit\n")
+
+    os.system(f"vivado -mode tcl -source build.tcl")
+    os.remove("build.tcl")
+
+if __name__ == "__main__":
+    main()
\ No newline at end of file