From 782f8977f9ad0dd60433bdd42c9bd5e939938941 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 26 Dec 2024 22:23:45 -0800
Subject: [PATCH] Update

---
 .gitignore                                |  1 +
 build/lib/build_fpga/__init__.py          |  5 --
 build/lib/build_fpga/build_fpga.py        | 27 --------
 build/lib/build_fpga/efinity.py           |  4 --
 build/lib/build_fpga/efinity/__init__.py  |  0
 build/lib/build_fpga/efinity/efinity.py   | 84 -----------------------
 build/lib/build_fpga/efinity/template.xml | 84 -----------------------
 pyproject.toml                            |  2 +-
 src/build_fpga/efinity/efinity.py         |  5 +-
 9 files changed, 5 insertions(+), 207 deletions(-)
 delete mode 100644 build/lib/build_fpga/__init__.py
 delete mode 100644 build/lib/build_fpga/build_fpga.py
 delete mode 100644 build/lib/build_fpga/efinity.py
 delete mode 100644 build/lib/build_fpga/efinity/__init__.py
 delete mode 100644 build/lib/build_fpga/efinity/efinity.py
 delete mode 100644 build/lib/build_fpga/efinity/template.xml

diff --git a/.gitignore b/.gitignore
index 7ce6162..461d36f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,5 +1,6 @@
 .venv
 dist
 *.egg*
+build/
 
 __pycache__
\ No newline at end of file
diff --git a/build/lib/build_fpga/__init__.py b/build/lib/build_fpga/__init__.py
deleted file mode 100644
index 936246c..0000000
--- a/build/lib/build_fpga/__init__.py
+++ /dev/null
@@ -1,5 +0,0 @@
-from .build_fpga import build_fpga_main
-
-def main():
-    build_fpga_main()
-
diff --git a/build/lib/build_fpga/build_fpga.py b/build/lib/build_fpga/build_fpga.py
deleted file mode 100644
index 73a0d0f..0000000
--- a/build/lib/build_fpga/build_fpga.py
+++ /dev/null
@@ -1,27 +0,0 @@
-import os
-import sys
-
-import argparse
-
-from rtl_manifest import rtl_manifest
-import yaml
-
-from .efinity import efinity
-
-def build_fpga_main():
-
-    parser = argparse.ArgumentParser(
-        prog="sim",
-        description="Tool to simulate"
-    )
-
-    parser.add_argument("yaml")
-
-    args = parser.parse_args()
-
-    with open(args.yaml) as cfg_file:
-        cfg = yaml.safe_load(cfg_file)
-
-    if (cfg["tool"] == "efinity"):
-        efinity.create_project(cfg)
-
diff --git a/build/lib/build_fpga/efinity.py b/build/lib/build_fpga/efinity.py
deleted file mode 100644
index a2d94e7..0000000
--- a/build/lib/build_fpga/efinity.py
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-def create_project(yaml):
-    
\ No newline at end of file
diff --git a/build/lib/build_fpga/efinity/__init__.py b/build/lib/build_fpga/efinity/__init__.py
deleted file mode 100644
index e69de29..0000000
diff --git a/build/lib/build_fpga/efinity/efinity.py b/build/lib/build_fpga/efinity/efinity.py
deleted file mode 100644
index 6fa6606..0000000
--- a/build/lib/build_fpga/efinity/efinity.py
+++ /dev/null
@@ -1,84 +0,0 @@
-import xml.etree.ElementTree as ET
-
-import os
-
-from rtl_manifest import read_sources
-
-TAG="{http://www.efinixinc.com/enf_proj}"
-
-
-def create_project(cfg):
-    script_dir = os.path.dirname(__file__)
-
-    print(cfg)
-
-    ET.register_namespace("efx", "http://www.efinixinc.com/enf_proj")
-    tree = ET.parse(os.path.join(script_dir, "template.xml"))
-    root = tree.getroot()
-
-    # Step 0: Add Project info
-    root.set("sw_version", cfg["prj_info"]["sw_version"])
-    root.set("name", cfg["prj_info"]["name"])
-
-    # Step 1: Add Device Info
-    device_info = root.find(f"{TAG}device_info")
-    assert device_info is not None
-
-    for attribute in ["family", "device", "timing_model"]:
-        element = ET.Element(f"efx:{attribute}", {"name": cfg["device_info"][attribute]})
-        device_info.append(element)
-
-    # Step 2: Add Design Info
-
-    # Part 1: Add attributes
-    design_info = root.find(f"{TAG}design_info")
-    assert design_info is not None
-    design_info.set("def_veri_version", cfg["design_info"]["verilog_version"])
-    # ignore vhdl :)
-    design_info.set("unified_flow", str(cfg["design_info"]["unified_flow"]).lower())    # hate yaml >:(
-
-    # Part 2: Add elements
-
-    top_module = ET.Element("efx:top_module", {"name": cfg["design_info"]["top_module"]})
-    design_info.append(top_module)
-
-    design_sources = read_sources(cfg["design_info"]["sources"])
-    for source in design_sources:
-        element = ET.Element("efx:design_file", {
-            "name": source,
-            "version": "default",
-            "library": "default"
-        })
-        design_info.append(element)
-
-    # Step 3: Add Constraints
-
-    constraint_info = root.find(f"{TAG}constraint_info")
-    assert constraint_info is not None
-
-    sdc_element = ET.Element("efx:sdc_file", {"name": cfg["constraint_info"]["sdc_file"]})
-    constraint_info.append(sdc_element)
-
-    # Step 4: Add ISF
-
-    isf_info = root.find(f"{TAG}isf_info")
-    assert isf_info is not None
-
-    isf_element = ET.Element("efx:isf_file", {"name": cfg["isf_info"]["isf_file"]})
-
-    # Step 5: Add Synthesis Options (Skipping options for now)
-
-    synthesis_options = root.find(f"{TAG}synthesis")
-    assert synthesis_options is not None
-
-    for macro_key, macro_value in cfg["synthesis_options"]["macros"].items():
-        expanded_value = os.path.expandvars(macro_value)
-        element = ET.Element("efx:defmacro", {"name": macro_key, "value": expanded_value})
-        synthesis_options.append(element)
-
-
-    ET.indent(tree, '    ')
-    tree.write("output.xml", encoding="utf-8", xml_declaration=False)
-
-if __name__ == "__main__":
-    create_project(None)
\ No newline at end of file
diff --git a/build/lib/build_fpga/efinity/template.xml b/build/lib/build_fpga/efinity/template.xml
deleted file mode 100644
index 48319de..0000000
--- a/build/lib/build_fpga/efinity/template.xml
+++ /dev/null
@@ -1,84 +0,0 @@
-<efx:project design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
-    <efx:device_info>
-    </efx:device_info>
-   <efx:design_info def_veri_version="verilog_2k" def_vhdl_version="vhdl_2008" unified_flow="false">
-    </efx:design_info>
-    <efx:constraint_info>
-    </efx:constraint_info>
-    <efx:isf_info>
-    </efx:isf_info>
-    <efx:sim_info />
-    <efx:misc_info />
-    <efx:ip_info />
-    <efx:synthesis tool_name="efx_map">
-        <efx:param name="work_dir" value="work_syn" value_type="e_string" />
-        <efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
-        <efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
-        <efx:param name="blackbox-error" value="1" value_type="e_option" />
-        <efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
-        <efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
-        <efx:param name="bram-push-tco-outreg" value="0" value_type="e_option" />
-        <efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
-        <efx:param name="fanout-limit" value="0" value_type="e_integer" />
-        <efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
-        <efx:param name="hdl-loop-limit" value="20000" value_type="e_integer" />
-        <efx:param name="infer-clk-enable" value="3" value_type="e_option" />
-        <efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
-        <efx:param name="max_ram" value="-1" value_type="e_integer" />
-        <efx:param name="max_mult" value="-1" value_type="e_integer" />
-        <efx:param name="min-sr-fanout" value="0" value_type="e_integer" />
-        <efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
-        <efx:param name="mode" value="speed" value_type="e_option" />
-        <efx:param name="mult-auto-pipeline" value="0" value_type="e_integer" />
-        <efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
-        <efx:param name="operator-sharing" value="0" value_type="e_option" />
-        <efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
-        <efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
-        <efx:param name="peri-syn-instantiation" value="1" value_type="e_option" />
-        <efx:param name="peri-syn-inference" value="1" value_type="e_option" />
-        <efx:param name="ram-decomp-mode" value="0" value_type="e_option" />
-        <efx:param name="retiming" value="1" value_type="e_option" />
-        <efx:param name="seq_opt" value="1" value_type="e_option" />
-        <efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
-        <efx:param name="use-logic-for-small-mem" value="64" value_type="e_integer" />
-        <efx:param name="use-logic-for-small-rom" value="64" value_type="e_integer" />
-        <efx:param name="max_threads" value="-1" value_type="e_integer" />
-        <efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
-        <efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
-    </efx:synthesis>
-    <efx:place_and_route tool_name="efx_pnr">
-        <efx:param name="work_dir" value="work_pnr" value_type="e_string" />
-        <efx:param name="verbose" value="off" value_type="e_bool" />
-        <efx:param name="load_delaym" value="on" value_type="e_bool" />
-        <efx:param name="optimization_level" value="TIMING_3" value_type="e_option" />
-        <efx:param name="seed" value="1" value_type="e_integer" />
-        <efx:param name="placer_effort_level" value="5" value_type="e_option" />
-        <efx:param name="max_threads" value="-1" value_type="e_integer" />
-        <efx:param name="print_critical_path" value="10" value_type="e_integer" />
-        <efx:param name="classic_flow" value="off" value_type="e_noarg" />
-    </efx:place_and_route>
-    <efx:bitstream_generation tool_name="efx_pgm">
-        <efx:param name="mode" value="active" value_type="e_string" />
-        <efx:param name="width" value="1" value_type="e_string" />
-        <efx:param name="enable_roms" value="smart" value_type="e_option" />
-        <efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
-        <efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
-        <efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
-        <efx:param name="bitstream_compression" value="on" value_type="e_bool" />
-        <efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
-        <efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
-        <efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
-        <efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
-        <efx:param name="cold_boot" value="off" value_type="e_bool" />
-        <efx:param name="cascade" value="off" value_type="e_option" />
-        <efx:param name="generate_bit" value="on" value_type="e_bool" />
-        <efx:param name="generate_bitbin" value="off" value_type="e_bool" />
-        <efx:param name="generate_hex" value="on" value_type="e_bool" />
-        <efx:param name="generate_hexbin" value="off" value_type="e_bool" />
-    </efx:bitstream_generation>
-    <efx:debugger>
-        <efx:param name="work_dir" value="work_dbg" value_type="e_string" />
-        <efx:param name="auto_instantiation" value="off" value_type="e_bool" />
-        <efx:param name="profile" value="NONE" value_type="e_string" />
-    </efx:debugger>
-</efx:project>
\ No newline at end of file
diff --git a/pyproject.toml b/pyproject.toml
index 7f32620..8de0a4e 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -35,7 +35,7 @@ name = "build-fpga"  # REQUIRED, is the only field that cannot be marked as dyna
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.2.0"  # REQUIRED, although can be dynamic
+version = "0.2.1"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:
diff --git a/src/build_fpga/efinity/efinity.py b/src/build_fpga/efinity/efinity.py
index 6fa6606..98b7ae1 100644
--- a/src/build_fpga/efinity/efinity.py
+++ b/src/build_fpga/efinity/efinity.py
@@ -10,7 +10,7 @@ TAG="{http://www.efinixinc.com/enf_proj}"
 def create_project(cfg):
     script_dir = os.path.dirname(__file__)
 
-    print(cfg)
+    # print(cfg)
 
     ET.register_namespace("efx", "http://www.efinixinc.com/enf_proj")
     tree = ET.parse(os.path.join(script_dir, "template.xml"))
@@ -65,6 +65,7 @@ def create_project(cfg):
     assert isf_info is not None
 
     isf_element = ET.Element("efx:isf_file", {"name": cfg["isf_info"]["isf_file"]})
+    isf_info.append(isf_element)
 
     # Step 5: Add Synthesis Options (Skipping options for now)
 
@@ -78,7 +79,7 @@ def create_project(cfg):
 
 
     ET.indent(tree, '    ')
-    tree.write("output.xml", encoding="utf-8", xml_declaration=False)
+    tree.write(f"{cfg["prj_info"]["name"]}.xml", encoding="utf-8", xml_declaration=False)
 
 if __name__ == "__main__":
     create_project(None)
\ No newline at end of file