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Byron Lathi
2024-12-26 22:01:11 -08:00
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.venv
dist
*.egg*
__pycache__

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image: python:latest
stages:
- build
- test
- deploy
build:
stage: build
rules:
- when: always
artifacts:
paths:
- ./dist
script:
- source init_env.sh
- python -m build
test:
stage: test
rules:
- when: always
script:
- source init_env.sh
- echo "Haha no tests yet"
deploy:
stage: deploy
rules:
# only run on MRs to main
# - if: $CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "master"
# run on commits to main
- if: $CI_COMMIT_BRANCH == "master"
script:
- source init_env.sh
- TWINE_PASSWORD=${CI_JOB_TOKEN} TWINE_USERNAME=gitlab-ci-token python -m twine upload --repository-url ${CI_API_V4_URL}/projects/${PACKAGE_PROJECT_ID}/packages/pypi dist/*

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Also add information on how to contact you by electronic and paper mail.
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
<program> Copyright (C) <year> <name of author>
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<https://www.gnu.org/licenses/>.
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<https://www.gnu.org/licenses/why-not-lgpl.html>.

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# Build FPGA

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from .build_fpga import build_fpga_main
def main():
build_fpga_main()

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import os
import sys
import argparse
from rtl_manifest import rtl_manifest
import yaml
from .efinity import efinity
def build_fpga_main():
parser = argparse.ArgumentParser(
prog="sim",
description="Tool to simulate"
)
parser.add_argument("yaml")
args = parser.parse_args()
with open(args.yaml) as cfg_file:
cfg = yaml.safe_load(cfg_file)
if (cfg["tool"] == "efinity"):
efinity.create_project(cfg)

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def create_project(yaml):

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import xml.etree.ElementTree as ET
import os
from rtl_manifest import read_sources
TAG="{http://www.efinixinc.com/enf_proj}"
def create_project(cfg):
script_dir = os.path.dirname(__file__)
print(cfg)
ET.register_namespace("efx", "http://www.efinixinc.com/enf_proj")
tree = ET.parse(os.path.join(script_dir, "template.xml"))
root = tree.getroot()
# Step 0: Add Project info
root.set("sw_version", cfg["prj_info"]["sw_version"])
root.set("name", cfg["prj_info"]["name"])
# Step 1: Add Device Info
device_info = root.find(f"{TAG}device_info")
assert device_info is not None
for attribute in ["family", "device", "timing_model"]:
element = ET.Element(f"efx:{attribute}", {"name": cfg["device_info"][attribute]})
device_info.append(element)
# Step 2: Add Design Info
# Part 1: Add attributes
design_info = root.find(f"{TAG}design_info")
assert design_info is not None
design_info.set("def_veri_version", cfg["design_info"]["verilog_version"])
# ignore vhdl :)
design_info.set("unified_flow", str(cfg["design_info"]["unified_flow"]).lower()) # hate yaml >:(
# Part 2: Add elements
top_module = ET.Element("efx:top_module", {"name": cfg["design_info"]["top_module"]})
design_info.append(top_module)
design_sources = read_sources(cfg["design_info"]["sources"])
for source in design_sources:
element = ET.Element("efx:design_file", {
"name": source,
"version": "default",
"library": "default"
})
design_info.append(element)
# Step 3: Add Constraints
constraint_info = root.find(f"{TAG}constraint_info")
assert constraint_info is not None
sdc_element = ET.Element("efx:sdc_file", {"name": cfg["constraint_info"]["sdc_file"]})
constraint_info.append(sdc_element)
# Step 4: Add ISF
isf_info = root.find(f"{TAG}isf_info")
assert isf_info is not None
isf_element = ET.Element("efx:isf_file", {"name": cfg["isf_info"]["isf_file"]})
# Step 5: Add Synthesis Options (Skipping options for now)
synthesis_options = root.find(f"{TAG}synthesis")
assert synthesis_options is not None
for macro_key, macro_value in cfg["synthesis_options"]["macros"].items():
expanded_value = os.path.expandvars(macro_value)
element = ET.Element("efx:defmacro", {"name": macro_key, "value": expanded_value})
synthesis_options.append(element)
ET.indent(tree, ' ')
tree.write("output.xml", encoding="utf-8", xml_declaration=False)
if __name__ == "__main__":
create_project(None)

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<efx:project design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
</efx:device_info>
<efx:design_info def_veri_version="verilog_2k" def_vhdl_version="vhdl_2008" unified_flow="false">
</efx:design_info>
<efx:constraint_info>
</efx:constraint_info>
<efx:isf_info>
</efx:isf_info>
<efx:sim_info />
<efx:misc_info />
<efx:ip_info />
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string" />
<efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
<efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
<efx:param name="blackbox-error" value="1" value_type="e_option" />
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="bram-push-tco-outreg" value="0" value_type="e_option" />
<efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
<efx:param name="fanout-limit" value="0" value_type="e_integer" />
<efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
<efx:param name="hdl-loop-limit" value="20000" value_type="e_integer" />
<efx:param name="infer-clk-enable" value="3" value_type="e_option" />
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
<efx:param name="max_ram" value="-1" value_type="e_integer" />
<efx:param name="max_mult" value="-1" value_type="e_integer" />
<efx:param name="min-sr-fanout" value="0" value_type="e_integer" />
<efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
<efx:param name="mode" value="speed" value_type="e_option" />
<efx:param name="mult-auto-pipeline" value="0" value_type="e_integer" />
<efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
<efx:param name="operator-sharing" value="0" value_type="e_option" />
<efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
<efx:param name="peri-syn-instantiation" value="1" value_type="e_option" />
<efx:param name="peri-syn-inference" value="1" value_type="e_option" />
<efx:param name="ram-decomp-mode" value="0" value_type="e_option" />
<efx:param name="retiming" value="1" value_type="e_option" />
<efx:param name="seq_opt" value="1" value_type="e_option" />
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
<efx:param name="use-logic-for-small-mem" value="64" value_type="e_integer" />
<efx:param name="use-logic-for-small-rom" value="64" value_type="e_integer" />
<efx:param name="max_threads" value="-1" value_type="e_integer" />
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string" />
<efx:param name="verbose" value="off" value_type="e_bool" />
<efx:param name="load_delaym" value="on" value_type="e_bool" />
<efx:param name="optimization_level" value="TIMING_3" value_type="e_option" />
<efx:param name="seed" value="1" value_type="e_integer" />
<efx:param name="placer_effort_level" value="5" value_type="e_option" />
<efx:param name="max_threads" value="-1" value_type="e_integer" />
<efx:param name="print_critical_path" value="10" value_type="e_integer" />
<efx:param name="classic_flow" value="off" value_type="e_noarg" />
</efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_string" />
<efx:param name="width" value="1" value_type="e_string" />
<efx:param name="enable_roms" value="smart" value_type="e_option" />
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
<efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
<efx:param name="bitstream_compression" value="on" value_type="e_bool" />
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
<efx:param name="cold_boot" value="off" value_type="e_bool" />
<efx:param name="cascade" value="off" value_type="e_option" />
<efx:param name="generate_bit" value="on" value_type="e_bool" />
<efx:param name="generate_bitbin" value="off" value_type="e_bool" />
<efx:param name="generate_hex" value="on" value_type="e_bool" />
<efx:param name="generate_hexbin" value="off" value_type="e_bool" />
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
<efx:param name="profile" value="NONE" value_type="e_string" />
</efx:debugger>
</efx:project>

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python3 -m venv .venv
source .venv/bin/activate
pip install -r requirements.txt

87
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<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="tx_fpga" description="" last_change="1735251500" sw_version="2024.2.294" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion" />
<efx:device name="T20F256" />
<efx:timing_model name="I4" />
</efx:device_info>
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008" unified_flow="false">
</efx:design_info>
<efx:constraint_info>
</efx:constraint_info>
<efx:isf_info>
</efx:isf_info>
<efx:sim_info />
<efx:misc_info />
<efx:ip_info />
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string" />
<efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
<efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
<efx:param name="blackbox-error" value="1" value_type="e_option" />
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="bram-push-tco-outreg" value="0" value_type="e_option" />
<efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
<efx:param name="fanout-limit" value="0" value_type="e_integer" />
<efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
<efx:param name="hdl-loop-limit" value="20000" value_type="e_integer" />
<efx:param name="infer-clk-enable" value="3" value_type="e_option" />
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
<efx:param name="max_ram" value="-1" value_type="e_integer" />
<efx:param name="max_mult" value="-1" value_type="e_integer" />
<efx:param name="min-sr-fanout" value="0" value_type="e_integer" />
<efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
<efx:param name="mode" value="speed" value_type="e_option" />
<efx:param name="mult-auto-pipeline" value="0" value_type="e_integer" />
<efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
<efx:param name="operator-sharing" value="0" value_type="e_option" />
<efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
<efx:param name="peri-syn-instantiation" value="0" value_type="e_option" />
<efx:param name="peri-syn-inference" value="0" value_type="e_option" />
<efx:param name="ram-decomp-mode" value="0" value_type="e_option" />
<efx:param name="retiming" value="1" value_type="e_option" />
<efx:param name="seq_opt" value="1" value_type="e_option" />
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
<efx:param name="use-logic-for-small-mem" value="64" value_type="e_integer" />
<efx:param name="use-logic-for-small-rom" value="64" value_type="e_integer" />
<efx:param name="max_threads" value="-1" value_type="e_integer" />
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string" />
<efx:param name="verbose" value="off" value_type="e_bool" />
<efx:param name="load_delaym" value="on" value_type="e_bool" />
<efx:param name="optimization_level" value="TIMING_3" value_type="e_option" />
<efx:param name="seed" value="1" value_type="e_integer" />
<efx:param name="placer_effort_level" value="5" value_type="e_option" />
<efx:param name="max_threads" value="-1" value_type="e_integer" />
<efx:param name="print_critical_path" value="10" value_type="e_integer" />
<efx:param name="classic_flow" value="off" value_type="e_noarg" />
</efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_string" />
<efx:param name="width" value="1" value_type="e_string" />
<efx:param name="enable_roms" value="smart" value_type="e_option" />
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
<efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
<efx:param name="bitstream_compression" value="on" value_type="e_bool" />
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
<efx:param name="cold_boot" value="off" value_type="e_bool" />
<efx:param name="cascade" value="off" value_type="e_option" />
<efx:param name="generate_bit" value="on" value_type="e_bool" />
<efx:param name="generate_bitbin" value="off" value_type="e_bool" />
<efx:param name="generate_hex" value="on" value_type="e_bool" />
<efx:param name="generate_hexbin" value="off" value_type="e_bool" />
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
<efx:param name="profile" value="NONE" value_type="e_string" />
</efx:debugger>
</efx:project>

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# Guide (user-friendly):
# https://packaging.python.org/en/latest/guides/writing-pyproject-toml/
# Specification (technical, formal):
# https://packaging.python.org/en/latest/specifications/pyproject-toml/
# Choosing a build backend:
# https://packaging.python.org/en/latest/tutorials/packaging-projects/#choosing-a-build-backend
[build-system]
# A list of packages that are needed to build your package:
requires = ["setuptools"] # REQUIRED if [build-system] table is used
# The name of the Python object that frontends will use to perform the build:
build-backend = "setuptools.build_meta" # If not defined, then legacy behavior can happen.
[project]
# This is the name of your project. The first time you publish this
# package, this name will be registered for you. It will determine how
# users can install this project, e.g.:
#
# $ pip install sampleproject
#
# And where it will live on PyPI: https://pypi.org/project/sampleproject/
#
# There are some restrictions on what makes a valid project name
# specification here:
# https://packaging.python.org/specifications/core-metadata/#name
name = "build-fpga" # REQUIRED, is the only field that cannot be marked as dynamic.
# Versions should comply with PEP 440:
# https://www.python.org/dev/peps/pep-0440/
#
# For a discussion on single-sourcing the version, see
# https://packaging.python.org/guides/single-sourcing-package-version/
# dynamic = ["version"]
version = "0.0.1" # REQUIRED, although can be dynamic
# This is a one-line description or tagline of what your project does. This
# corresponds to the "Summary" metadata field:
# https://packaging.python.org/specifications/core-metadata/#summary
description = "Tool for reading list files and turning them into paths"
# This is an optional longer description of your project that represents
# the body of text which users will see when they visit PyPI.
#
# Often, this is the same as your README, so you can just read it in from
# that file directly.
#
# This field corresponds to the "Description" metadata field:
# https://packaging.python.org/specifications/core-metadata/#description-optional
readme = "README.md"
# Specify which Python versions you support. In contrast to the
# 'Programming Language' classifiers in this file, 'pip install' will check this
# and refuse to install the project if the version does not match. See
# https://packaging.python.org/guides/distributing-packages-using-setuptools/#python-requires
requires-python = ">=3.8"
# This is either text indicating the license for the distribution, or a file
# that contains the license.
# https://packaging.python.org/en/latest/specifications/core-metadata/#license
license = {file = "LICENSE.txt"}
# This field adds keywords for your project which will appear on the
# project page. What does your project relate to?
#
# Note that this is a list of additional keywords, separated
# by commas, to be used to assist searching for the distribution in a
# larger catalog.
keywords = ["build_fpga", "setuptools", "development", "verilog", "system-verilog"]
# This should be your name or the name of the organization who originally
# authored the project, and a valid email address corresponding to the name
# listed.
authors = [
{name = "Byron Lathi", email = "byron@byronlathi.com" }
]
# This should be your name or the names of the organization who currently
# maintains the project, and a valid email address corresponding to the name
# listed.
# maintainers = [
# {name = "A. Great Maintainer", email = "maintainer@example.com" }
# ]
# Classifiers help users find your project by categorizing it.
#
# For a list of valid classifiers, see https://pypi.org/classifiers/
classifiers = [
# How mature is this project? Common values are
# 3 - Alpha
# 4 - Beta
# 5 - Production/Stable
"Development Status :: 3 - Alpha",
# Indicate who your project is intended for
"Intended Audience :: Developers",
"Topic :: Hardware Development :: Build Tools",
# Pick your license as you wish
# "License :: OSI Approved :: MIT License",
# Specify the Python versions you support here. In particular, ensure
# that you indicate you support Python 3. These classifiers are *not*
# checked by "pip install". See instead "requires-python" key in this file.
"Programming Language :: Python :: 3",
"Programming Language :: Python :: 3.8",
"Programming Language :: Python :: 3.9",
"Programming Language :: Python :: 3.10",
"Programming Language :: Python :: 3.11",
"Programming Language :: Python :: 3.12",
"Programming Language :: Python :: 3 :: Only",
]
# This field lists other packages that your project depends on to run.
# Any package you put here will be installed by pip when your project is
# installed, so they must be valid existing projects.
#
# For an analysis of this field vs pip's requirements files see:
# https://packaging.python.org/discussions/install-requires-vs-requirements/
dependencies = [
"pyyaml",
"rtl-manifest"
]
# List additional groups of dependencies here (e.g. development
# dependencies). Users will be able to install these using the "extras"
# syntax, for example:
#
# $ pip install sampleproject[dev]
#
# Optional dependencies the project provides. These are commonly
# referred to as "extras". For a more extensive definition see:
# https://packaging.python.org/en/latest/specifications/dependency-specifiers/#extras
# [project.optional-dependencies]
# dev = ["check-manifest"]
# test = ["coverage"]
# List URLs that are relevant to your project
#
# This field corresponds to the "Project-URL" and "Home-Page" metadata fields:
# https://packaging.python.org/specifications/core-metadata/#project-url-multiple-use
# https://packaging.python.org/specifications/core-metadata/#home-page-optional
#
# Examples listed include a pattern for specifying where the package tracks
# issues, where the source is hosted, where to say thanks to the package
# maintainers, and where to support the project financially. The key is
# what's used to render the link text on PyPI.
# [project.urls]
# "Homepage" = "https://github.com/pypa/sampleproject"
# "Bug Reports" = "https://github.com/pypa/sampleproject/issues"
# "Funding" = "https://donate.pypi.org"
# "Say Thanks!" = "http://saythanks.io/to/example"
# "Source" = "https://github.com/pypa/sampleproject/"
# The following would provide a command line executable called `sample`
# which executes the function `main` from this package when invoked.
[project.scripts]
build_fpga = "build_fpga:main"
# This is configuration specific to the `setuptools` build backend.
# If you are using a different build backend, you will need to change this.
[tool.setuptools]
# If there are data files included in your packages that need to be
# installed, specify them here.
package-data = {"build_fpga" = ["efinity/template.xml"]}

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setuptools
wheel
build
twine

5
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from .build_fpga import build_fpga_main
def main():
build_fpga_main()

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src/build_fpga/build_fpga.py Normal file
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import os
import sys
import argparse
from rtl_manifest import rtl_manifest
import yaml
from .efinity import efinity
def build_fpga_main():
parser = argparse.ArgumentParser(
prog="sim",
description="Tool to simulate"
)
parser.add_argument("yaml")
args = parser.parse_args()
with open(args.yaml) as cfg_file:
cfg = yaml.safe_load(cfg_file)
if (cfg["tool"] == "efinity"):
efinity.create_project(cfg)

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src/build_fpga/efinity/__init__.py Normal file
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src/build_fpga/efinity/efinity.py Normal file
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import xml.etree.ElementTree as ET
import os
from rtl_manifest import read_sources
TAG="{http://www.efinixinc.com/enf_proj}"
def create_project(cfg):
script_dir = os.path.dirname(__file__)
print(cfg)
ET.register_namespace("efx", "http://www.efinixinc.com/enf_proj")
tree = ET.parse(os.path.join(script_dir, "template.xml"))
root = tree.getroot()
# Step 0: Add Project info
root.set("sw_version", cfg["prj_info"]["sw_version"])
root.set("name", cfg["prj_info"]["name"])
# Step 1: Add Device Info
device_info = root.find(f"{TAG}device_info")
assert device_info is not None
for attribute in ["family", "device", "timing_model"]:
element = ET.Element(f"efx:{attribute}", {"name": cfg["device_info"][attribute]})
device_info.append(element)
# Step 2: Add Design Info
# Part 1: Add attributes
design_info = root.find(f"{TAG}design_info")
assert design_info is not None
design_info.set("def_veri_version", cfg["design_info"]["verilog_version"])
# ignore vhdl :)
design_info.set("unified_flow", str(cfg["design_info"]["unified_flow"]).lower()) # hate yaml >:(
# Part 2: Add elements
top_module = ET.Element("efx:top_module", {"name": cfg["design_info"]["top_module"]})
design_info.append(top_module)
design_sources = read_sources(cfg["design_info"]["sources"])
for source in design_sources:
element = ET.Element("efx:design_file", {
"name": source,
"version": "default",
"library": "default"
})
design_info.append(element)
# Step 3: Add Constraints
constraint_info = root.find(f"{TAG}constraint_info")
assert constraint_info is not None
sdc_element = ET.Element("efx:sdc_file", {"name": cfg["constraint_info"]["sdc_file"]})
constraint_info.append(sdc_element)
# Step 4: Add ISF
isf_info = root.find(f"{TAG}isf_info")
assert isf_info is not None
isf_element = ET.Element("efx:isf_file", {"name": cfg["isf_info"]["isf_file"]})
# Step 5: Add Synthesis Options (Skipping options for now)
synthesis_options = root.find(f"{TAG}synthesis")
assert synthesis_options is not None
for macro_key, macro_value in cfg["synthesis_options"]["macros"].items():
expanded_value = os.path.expandvars(macro_value)
element = ET.Element("efx:defmacro", {"name": macro_key, "value": expanded_value})
synthesis_options.append(element)
ET.indent(tree, ' ')
tree.write("output.xml", encoding="utf-8", xml_declaration=False)
if __name__ == "__main__":
create_project(None)

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<efx:project design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
</efx:device_info>
<efx:design_info def_veri_version="verilog_2k" def_vhdl_version="vhdl_2008" unified_flow="false">
</efx:design_info>
<efx:constraint_info>
</efx:constraint_info>
<efx:isf_info>
</efx:isf_info>
<efx:sim_info />
<efx:misc_info />
<efx:ip_info />
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string" />
<efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
<efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
<efx:param name="blackbox-error" value="1" value_type="e_option" />
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="bram-push-tco-outreg" value="0" value_type="e_option" />
<efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
<efx:param name="fanout-limit" value="0" value_type="e_integer" />
<efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
<efx:param name="hdl-loop-limit" value="20000" value_type="e_integer" />
<efx:param name="infer-clk-enable" value="3" value_type="e_option" />
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
<efx:param name="max_ram" value="-1" value_type="e_integer" />
<efx:param name="max_mult" value="-1" value_type="e_integer" />
<efx:param name="min-sr-fanout" value="0" value_type="e_integer" />
<efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
<efx:param name="mode" value="speed" value_type="e_option" />
<efx:param name="mult-auto-pipeline" value="0" value_type="e_integer" />
<efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
<efx:param name="operator-sharing" value="0" value_type="e_option" />
<efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
<efx:param name="peri-syn-instantiation" value="1" value_type="e_option" />
<efx:param name="peri-syn-inference" value="1" value_type="e_option" />
<efx:param name="ram-decomp-mode" value="0" value_type="e_option" />
<efx:param name="retiming" value="1" value_type="e_option" />
<efx:param name="seq_opt" value="1" value_type="e_option" />
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
<efx:param name="use-logic-for-small-mem" value="64" value_type="e_integer" />
<efx:param name="use-logic-for-small-rom" value="64" value_type="e_integer" />
<efx:param name="max_threads" value="-1" value_type="e_integer" />
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string" />
<efx:param name="verbose" value="off" value_type="e_bool" />
<efx:param name="load_delaym" value="on" value_type="e_bool" />
<efx:param name="optimization_level" value="TIMING_3" value_type="e_option" />
<efx:param name="seed" value="1" value_type="e_integer" />
<efx:param name="placer_effort_level" value="5" value_type="e_option" />
<efx:param name="max_threads" value="-1" value_type="e_integer" />
<efx:param name="print_critical_path" value="10" value_type="e_integer" />
<efx:param name="classic_flow" value="off" value_type="e_noarg" />
</efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_string" />
<efx:param name="width" value="1" value_type="e_string" />
<efx:param name="enable_roms" value="smart" value_type="e_option" />
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
<efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
<efx:param name="bitstream_compression" value="on" value_type="e_bool" />
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
<efx:param name="cold_boot" value="off" value_type="e_bool" />
<efx:param name="cascade" value="off" value_type="e_option" />
<efx:param name="generate_bit" value="on" value_type="e_bool" />
<efx:param name="generate_bitbin" value="off" value_type="e_bool" />
<efx:param name="generate_hex" value="on" value_type="e_bool" />
<efx:param name="generate_hexbin" value="off" value_type="e_bool" />
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
<efx:param name="profile" value="NONE" value_type="e_string" />
</efx:debugger>
</efx:project>

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test/Makefile Normal file
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.PHONY: clean
clean:
rm -rf *.xml
rm -rf ip
rm -rf work*
rm -rf outflow

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test/sources.list Normal file
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src/sources.list

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test/src/sources.list Normal file
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test_top.sv
test_module.sv

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test/src/test_module.sv Normal file
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module test_module (
input i_clk,
input i_rst,
output logic [31:0] o_count
);
logic [31:0] counter;
always_ff @(posedge i_clk) begin
if (i_rst) begin
counter <= '0;
end else begin
counter <= counter + 1;
end
end
assign o_count = counter;
endmodule

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test/src/test_top.sv Normal file
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module test_top (
input i_clk,
input i_rst,
output o_led
);
logic [31:0] count;
test_module u_test_module(
.i_clk (i_clk),
.i_rst (i_rst),
.o_count (count)
);
assign o_led = count[31];
endmodule

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test/test.yaml Normal file
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tool: "efinity"
prj_info:
name: "test"
sw_version: "2024.2.294"
device_info:
family: "Trion"
device: "T20F256"
timing_model: "I4"
design_info:
unified_flow: True
verilog_version: "sv_09"
sources: "sources.list"
top_module: "test_top"
constraint_info:
sdc_file: "constraints/constraints.sdc"
isf_info:
isf_file: "placement.isf"
synthesis_options:
macros:
IFFT_PATH: "$REPO_TOP/src/sub/tx/sub/tx_dataplane/sub/ifft/fft-core/"
pnr_options:
optimization_level: "TIMING_3"
placer_effort_level: 5
pgm_options:
debugger_options: