Fix multiple xdc files

pyproject.toml

@@ -35,7 +35,7 @@ name = "build-fpga"  # REQUIRED, is the only field that cannot be marked as dyna
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.4.0"  # REQUIRED, although can be dynamic
+version = "0.4.2"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:

src/build_fpga/efinity/efinity.py

@@ -84,6 +84,5 @@ def create_project(cfg, filename):
 def build_project(cfg):
     name = f"{cfg['prj_info']['name']}.xml"
     create_project(cfg, name)
-    os.mkdir("output")
     os.system(f"efx_run --prj {name} --output_dir outflow --work_dir work")
 

src/build_fpga/vivado/vivado.py

@@ -36,7 +36,7 @@ def build_nonprj(cfg):
 
         f.write(f"read_verilog -sv {' '.join(verilog_sources)}\n")
         f.write(f"read_ip \"{' '.join(xci_sources)}\"\n")
-        f.write(f"read_xdc {' '.join(xdc_sources)}\n")
+        f.write(f"read_xdc \"{' '.join(xdc_sources)}\"\n")
         
         f.write(f"synth_ip [get_ips *]\n")
         f.write(f"synth_design -top {top} -directive {synth_directive}\n")
@@ -54,5 +54,5 @@ def build_nonprj(cfg):
         f.write(f"write_bitstream -force $outputDir/{top}.bit\n")
         f.write(f"exit\n")
 
-    os.system(f"vivado -mode tcl -source build.tcl")
+    os.system(f"vivado -nolog -nojournal -mode tcl -source build.tcl")
     os.remove("build.tcl")