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build_fpga/test/test.yaml
2024-12-26 22:01:11 -08:00

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YAML

tool: "efinity"
prj_info:
name: "test"
sw_version: "2024.2.294"
device_info:
family: "Trion"
device: "T20F256"
timing_model: "I4"
design_info:
unified_flow: True
verilog_version: "sv_09"
sources: "sources.list"
top_module: "test_top"
constraint_info:
sdc_file: "constraints/constraints.sdc"
isf_info:
isf_file: "placement.isf"
synthesis_options:
macros:
IFFT_PATH: "$REPO_TOP/src/sub/tx/sub/tx_dataplane/sub/ifft/fft-core/"
pnr_options:
optimization_level: "TIMING_3"
placer_effort_level: 5
pgm_options:
debugger_options: