60 lines
2.1 KiB
Diff
60 lines
2.1 KiB
Diff
From 8c47453e7d8a36371bd50b871492e4299e69ab4a Mon Sep 17 00:00:00 2001
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From: Mohamad Noor Alim Hussin <mnalim@efinixinc.com>
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Date: Thu, 24 Feb 2022 12:50:40 +0800
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Subject: [PATCH] numpy/core: Define RISCV-32 support
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Helps compile on riscv32
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Upstream-Status: Submitted [https://github.com/numpy/numpy/pull/17780]
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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Signed-off-by: Mohamad Noor Alim Hussin <mnalim@efinixinc.com>
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---
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numpy/core/include/numpy/npy_cpu.h | 9 +++++++--
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numpy/core/include/numpy/npy_endian.h | 3 ++-
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2 files changed, 9 insertions(+), 3 deletions(-)
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diff --git a/numpy/core/include/numpy/npy_cpu.h b/numpy/core/include/numpy/npy_cpu.h
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index 5edd8f42e..685f30906 100644
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--- a/numpy/core/include/numpy/npy_cpu.h
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+++ b/numpy/core/include/numpy/npy_cpu.h
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@@ -18,6 +18,7 @@
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* NPY_CPU_ARCEL
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* NPY_CPU_ARCEB
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* NPY_CPU_RISCV64
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+ * NPY_CPU_RISCV32
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*/
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#ifndef _NPY_CPUARCH_H_
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#define _NPY_CPUARCH_H_
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@@ -100,8 +101,12 @@
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#define NPY_CPU_ARCEL
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#elif defined(__arc__) && defined(__BIG_ENDIAN__)
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#define NPY_CPU_ARCEB
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-#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64
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- #define NPY_CPU_RISCV64
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+#elif defined(__riscv)
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+ #if __riscv_xlen == 64
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+ #define NPY_CPU_RISCV64
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+ #elif __riscv_xlen == 32
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+ #define NPY_CPU_RISCV32
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+ #endif
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#else
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#error Unknown CPU, please report this to numpy maintainers with \
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information about your platform (OS, CPU and compiler)
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diff --git a/numpy/core/include/numpy/npy_endian.h b/numpy/core/include/numpy/npy_endian.h
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index 44cdffd14..c93e7cbaf 100644
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--- a/numpy/core/include/numpy/npy_endian.h
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+++ b/numpy/core/include/numpy/npy_endian.h
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@@ -48,7 +48,8 @@
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|| defined(NPY_CPU_MIPSEL) \
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|| defined(NPY_CPU_PPC64LE) \
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|| defined(NPY_CPU_ARCEL) \
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- || defined(NPY_CPU_RISCV64)
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+ || defined(NPY_CPU_RISCV64) \
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+ || defined(NPY_CPU_RISCV32)
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#define NPY_BYTE_ORDER NPY_LITTLE_ENDIAN
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#elif defined(NPY_CPU_PPC) \
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|| defined(NPY_CPU_SPARC) \
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--
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2.17.1
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