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Fixed inline assembler problems with instructions where implicit means

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actually accumulator addressing. These went through and caused the
optimizer to behave strangely.


git-svn-id: svn://svn.cc65.org/cc65/trunk@3164 b7a2c559-68d2-44c3-8de9-860c34a00d81
This commit is contained in:
cuz
2004-07-18 09:34:52 +00:00
parent 9b2834ef7e
commit 1fb5967496
3 changed files with 31 additions and 26 deletions
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8
src/cc65/codeseg.c
View File

@@ -289,8 +289,12 @@ static CodeEntry* ParseInsn (CodeSeg* S, LineInfo* LI, const char* L)
switch (*L) { switch (*L) {
case '\0': case '\0':
/* Implicit */ /* Implicit or accu */
AM = AM65_IMP; if (OPC->Info & OF_NOIMP) {
AM = AM65_ACC;
} else {
AM = AM65_IMP;
}
break; break;
case '#': case '#':

48
src/cc65/opcodes.c
View File

@@ -63,21 +63,21 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */ 0, /* size */
REG_A, /* use */ REG_A, /* use */
REG_A, /* chg */ REG_A, /* chg */
OF_SETF /* flags */ OF_SETF /* flags */
}, },
{ OP65_AND, /* opcode */ { OP65_AND, /* opcode */
"and", /* mnemonic */ "and", /* mnemonic */
0, /* size */ 0, /* size */
REG_A, /* use */ REG_A, /* use */
REG_A, /* chg */ REG_A, /* chg */
OF_SETF /* flags */ OF_SETF /* flags */
}, },
{ OP65_ASL, /* opcode */ { OP65_ASL, /* opcode */
"asl", /* mnemonic */ "asl", /* mnemonic */
0, /* size */ 0, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_SETF /* flags */ OF_SETF | OF_NOIMP /* flags */
}, },
{ OP65_BCC, /* opcode */ { OP65_BCC, /* opcode */
"bcc", /* mnemonic */ "bcc", /* mnemonic */
@@ -154,7 +154,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
2, /* size */ 2, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_CBRA /* flags */ OF_CBRA /* flags */
}, },
{ OP65_CLC, /* opcode */ { OP65_CLC, /* opcode */
"clc", /* mnemonic */ "clc", /* mnemonic */
@@ -217,7 +217,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */ 0, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_SETF /* flags */ OF_SETF | OF_NOIMP /* flags */
}, },
{ OP65_DEX, /* opcode */ { OP65_DEX, /* opcode */
"dex", /* mnemonic */ "dex", /* mnemonic */
@@ -238,7 +238,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */ 0, /* size */
REG_A, /* use */ REG_A, /* use */
REG_A, /* chg */ REG_A, /* chg */
OF_SETF /* flags */ OF_SETF /* flags */
}, },
{ OP65_INA, /* opcode */ { OP65_INA, /* opcode */
"ina", /* mnemonic */ "ina", /* mnemonic */
@@ -252,7 +252,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */ 0, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_SETF /* flags */ OF_SETF | OF_NOIMP /* flags */
}, },
{ OP65_INX, /* opcode */ { OP65_INX, /* opcode */
"inx", /* mnemonic */ "inx", /* mnemonic */
@@ -329,7 +329,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
5, /* size */ 5, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_CBRA | OF_LBRA /* flags */ OF_CBRA | OF_LBRA /* flags */
}, },
{ OP65_JVS, /* opcode */ { OP65_JVS, /* opcode */
"jvs", /* mnemonic */ "jvs", /* mnemonic */
@@ -364,7 +364,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */ 0, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_SETF /* flags */ OF_SETF | OF_NOIMP /* flags */
}, },
{ OP65_NOP, /* opcode */ { OP65_NOP, /* opcode */
"nop", /* mnemonic */ "nop", /* mnemonic */
@@ -420,7 +420,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
1, /* size */ 1, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_NONE /* flags */ OF_NONE /* flags */
}, },
{ OP65_PLX, /* opcode */ { OP65_PLX, /* opcode */
"plx", /* mnemonic */ "plx", /* mnemonic */
@@ -441,14 +441,14 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */ 0, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_SETF /* flags */ OF_SETF | OF_NOIMP /* flags */
}, },
{ OP65_ROR, /* opcode */ { OP65_ROR, /* opcode */
"ror", /* mnemonic */ "ror", /* mnemonic */
0, /* size */ 0, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_SETF /* flags */ OF_SETF | OF_NOIMP /* flags */
}, },
/* Mark RTI as "uses all registers but doesn't change them", so the /* Mark RTI as "uses all registers but doesn't change them", so the
* optimizer won't remove preceeding loads. * optimizer won't remove preceeding loads.
@@ -458,70 +458,70 @@ const OPCDesc OPCTable[OP65_COUNT] = {
1, /* size */ 1, /* size */
REG_AXY, /* use */ REG_AXY, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_RET /* flags */ OF_RET /* flags */
}, },
{ OP65_RTS, /* opcode */ { OP65_RTS, /* opcode */
"rts", /* mnemonic */ "rts", /* mnemonic */
1, /* size */ 1, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_RET /* flags */ OF_RET /* flags */
}, },
{ OP65_SBC, /* opcode */ { OP65_SBC, /* opcode */
"sbc", /* mnemonic */ "sbc", /* mnemonic */
0, /* size */ 0, /* size */
REG_A, /* use */ REG_A, /* use */
REG_A, /* chg */ REG_A, /* chg */
OF_SETF /* flags */ OF_SETF /* flags */
}, },
{ OP65_SEC, /* opcode */ { OP65_SEC, /* opcode */
"sec", /* mnemonic */ "sec", /* mnemonic */
1, /* size */ 1, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_NONE /* flags */ OF_NONE /* flags */
}, },
{ OP65_SED, /* opcode */ { OP65_SED, /* opcode */
"sed", /* mnemonic */ "sed", /* mnemonic */
1, /* size */ 1, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_NONE /* flags */ OF_NONE /* flags */
}, },
{ OP65_SEI, /* opcode */ { OP65_SEI, /* opcode */
"sei", /* mnemonic */ "sei", /* mnemonic */
1, /* size */ 1, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_NONE /* flags */ OF_NONE /* flags */
}, },
{ OP65_STA, /* opcode */ { OP65_STA, /* opcode */
"sta", /* mnemonic */ "sta", /* mnemonic */
0, /* size */ 0, /* size */
REG_A, /* use */ REG_A, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_STORE /* flags */ OF_STORE /* flags */
}, },
{ OP65_STX, /* opcode */ { OP65_STX, /* opcode */
"stx", /* mnemonic */ "stx", /* mnemonic */
0, /* size */ 0, /* size */
REG_X, /* use */ REG_X, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_STORE /* flags */ OF_STORE /* flags */
}, },
{ OP65_STY, /* opcode */ { OP65_STY, /* opcode */
"sty", /* mnemonic */ "sty", /* mnemonic */
0, /* size */ 0, /* size */
REG_Y, /* use */ REG_Y, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_STORE /* flags */ OF_STORE /* flags */
}, },
{ OP65_STZ, /* opcode */ { OP65_STZ, /* opcode */
"stz", /* mnemonic */ "stz", /* mnemonic */
0, /* size */ 0, /* size */
REG_NONE, /* use */ REG_NONE, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_STORE /* flags */ OF_STORE /* flags */
}, },
{ OP65_TAX, /* opcode */ { OP65_TAX, /* opcode */
"tax", /* mnemonic */ "tax", /* mnemonic */
@@ -549,7 +549,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */ 0, /* size */
REG_A, /* use */ REG_A, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_SETF /* flags */ OF_SETF /* flags */
}, },
{ OP65_TSX, /* opcode */ { OP65_TSX, /* opcode */
"tsx", /* mnemonic */ "tsx", /* mnemonic */
@@ -570,7 +570,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
1, /* size */ 1, /* size */
REG_X, /* use */ REG_X, /* use */
REG_NONE, /* chg */ REG_NONE, /* chg */
OF_XFR /* flags */ OF_XFR /* flags */
}, },
{ OP65_TYA, /* opcode */ { OP65_TYA, /* opcode */
"tya", /* mnemonic */ "tya", /* mnemonic */

1
src/cc65/opcodes.h
View File

@@ -174,6 +174,7 @@ typedef enum {
#define OF_REG_INCDEC 0x0400U /* A register increment or decrement */ #define OF_REG_INCDEC 0x0400U /* A register increment or decrement */
#define OF_SETF 0x0800U /* Insn will set all load flags (not carry) */ #define OF_SETF 0x0800U /* Insn will set all load flags (not carry) */
#define OF_CMP 0x1000U /* A compare A/X/Y instruction */ #define OF_CMP 0x1000U /* A compare A/X/Y instruction */
#define OF_NOIMP 0x2000U /* Implicit addressing mode is actually A */
/* Combined infos */ /* Combined infos */
#define OF_BRA (OF_UBRA | OF_CBRA) /* Operation is a jump/branch */ #define OF_BRA (OF_UBRA | OF_CBRA) /* Operation is a jump/branch */