From 20e7c54fa36f2b4a1746b625662b71aa729d4f4c Mon Sep 17 00:00:00 2001 From: mrdudz Date: Mon, 16 Jun 2025 20:32:54 +0200 Subject: [PATCH] more m740 fixes, makes the regression test work --- src/ca65/ea65.c | 9 +- src/ca65/instr.c | 229 ++++++--- src/ca65/instr.h | 55 +- src/da65/handler.c | 12 +- src/da65/opcm740.c | 7 +- test/asm/opcodes/m740-opcodes.ref | Bin 0 -> 768 bytes test/asm/opcodes/m740-opcodes.s | 823 ++++++++++++++++++++---------- 7 files changed, 759 insertions(+), 376 deletions(-) create mode 100644 test/asm/opcodes/m740-opcodes.ref diff --git a/src/ca65/ea65.c b/src/ca65/ea65.c index 965d15b2d..da11b268a 100644 --- a/src/ca65/ea65.c +++ b/src/ca65/ea65.c @@ -186,10 +186,11 @@ void GetEA (EffAddr* A) /* Remaining stuff: ** - ** adr - ** adr,x - ** adr,y - ** adr,s + ** addr + ** addr, x + ** addr, y + ** addr, s + ** addr, relative addr */ A->Expr = Expression (); diff --git a/src/ca65/instr.c b/src/ca65/instr.c index 1b33bcd7d..9fffd312f 100644 --- a/src/ca65/instr.c +++ b/src/ca65/instr.c @@ -138,6 +138,11 @@ static void PutJSR816 (const InsDesc* Ins); ** Allowing the long_jsr_jmp_rts feature to permit a long JSR. */ +static void PutJSR_m740 (const InsDesc* Ins); +/* Handle the JSR instruction for the m740 +** Allowing the special page feature. +*/ + static void PutRTS (const InsDesc* Ins attribute ((unused))); /* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if ** the enclosing scope is FAR, but only if the long_jsr_jmp_rts feature applies. @@ -1053,6 +1058,9 @@ static const struct { } }; +/* CAUTION: in the pdf $1a is dec a, and $3a is inc a - if that is really the case, + * the table below (and the handler) should be fixed and this notice removed */ + /* Instruction table for the m740 CPU */ static const struct { unsigned Count; @@ -1091,82 +1099,82 @@ static const struct { { "BRK", 0x00000001, 0x00, 0, PutAll }, { "BVC", 0x00020000, 0x50, 0, PutPCRel8 }, { "BVS", 0x00020000, 0x70, 0, PutPCRel8 }, - { "CLB0", 0x0000006, 0x1b, 10, PutAll }, - { "CLB1", 0x0000006, 0x3b, 10, PutAll }, - { "CLB2", 0x0000006, 0x5b, 10, PutAll }, - { "CLB3", 0x0000006, 0x7b, 10, PutAll }, - { "CLB4", 0x0000006, 0x9b, 10, PutAll }, - { "CLB5", 0x0000006, 0xbb, 10, PutAll }, - { "CLB6", 0x0000006, 0xdb, 10, PutAll }, - { "CLB7", 0x0000006, 0xfb, 10, PutAll }, - { "CLC", 0x0000001, 0x18, 0, PutAll }, - { "CLD", 0x0000001, 0xd8, 0, PutAll }, - { "CLI", 0x0000001, 0x58, 0, PutAll }, - { "CLT", 0x0000001, 0x12, 0, PutAll }, - { "CLV", 0x0000001, 0xb8, 0, PutAll }, - { "CMP", 0x080A26C, 0xc0, 0, PutAll }, - { "COM", 0x0000004, 0x44, 1, PutAll }, - { "CPX", 0x080000C, 0xe0, 1, PutAll }, - { "CPY", 0x080000C, 0xc0, 1, PutAll }, - { "DEC", 0x000006F, 0x00, 3, PutAll }, - { "DEX", 0x0000001, 0xca, 0, PutAll }, - { "DEY", 0x0000001, 0x88, 0, PutAll }, - { "EOR", 0x080A26C, 0x40, 0, PutAll }, - { "FST", 0x0000001, 0xe2, 0, PutAll }, - { "INC", 0x000006f, 0x00, 4, PutAll }, - { "INX", 0x0000001, 0xe8, 0, PutAll }, - { "INY", 0x0000001, 0xc8, 0, PutAll }, - { "JMP", 0x0000C08, 0x00, 12, PutAll }, - { "JSR", 0x0080808, 0x00, 13, PutAll }, - { "LDA", 0x080A26C, 0xa0, 0, PutAll }, + { "CLB0", 0x00000006, 0x1b, 10, PutAll }, + { "CLB1", 0x00000006, 0x3b, 10, PutAll }, + { "CLB2", 0x00000006, 0x5b, 10, PutAll }, + { "CLB3", 0x00000006, 0x7b, 10, PutAll }, + { "CLB4", 0x00000006, 0x9b, 10, PutAll }, + { "CLB5", 0x00000006, 0xbb, 10, PutAll }, + { "CLB6", 0x00000006, 0xdb, 10, PutAll }, + { "CLB7", 0x00000006, 0xfb, 10, PutAll }, + { "CLC", 0x00000001, 0x18, 0, PutAll }, + { "CLD", 0x00000001, 0xd8, 0, PutAll }, + { "CLI", 0x00000001, 0x58, 0, PutAll }, + { "CLT", 0x00000001, 0x12, 0, PutAll }, + { "CLV", 0x00000001, 0xb8, 0, PutAll }, + { "CMP", 0x0080A26C, 0xc0, 0, PutAll }, + { "COM", 0x00000004, 0x44, 1, PutAll }, + { "CPX", 0x0080000C, 0xe0, 1, PutAll }, + { "CPY", 0x0080000C, 0xc0, 1, PutAll }, + { "DEC", 0x0000006F, 0x00, 3, PutAll }, + { "DEX", 0x00000001, 0xca, 0, PutAll }, + { "DEY", 0x00000001, 0x88, 0, PutAll }, + { "EOR", 0x0080A26C, 0x40, 0, PutAll }, + { "FST", 0x00000001, 0xe2, 0, PutAll }, + { "INC", 0x0000006f, 0x00, 4, PutAll }, + { "INX", 0x00000001, 0xe8, 0, PutAll }, + { "INY", 0x00000001, 0xc8, 0, PutAll }, + { "JMP", 0x00000C08, 0x00, 12, PutAll }, + { "JSR", 0x20000408, 0x00, 13, PutJSR_m740 }, + { "LDA", 0x0080A26C, 0xa0, 0, PutAll }, { "LDM", 0x10000000, 0x3c, 0, PutLDM_m740 }, - { "LDX", 0x080030C, 0xa2, 1, PutAll }, - { "LDY", 0x080006C, 0xa0, 1, PutAll }, - { "LSR", 0x000006F, 0x42, 1, PutAll }, - { "NOP", 0x0000001, 0xea, 0, PutAll }, - { "ORA", 0x080A26C, 0x00, 0, PutAll }, - { "PHA", 0x0000001, 0x48, 0, PutAll }, - { "PHP", 0x0000001, 0x08, 0, PutAll }, - { "PLA", 0x0000001, 0x68, 0, PutAll }, - { "PLP", 0x0000001, 0x28, 0, PutAll }, - { "RMB0", 0x0000006, 0x1b, 10, PutAll }, - { "RMB1", 0x0000006, 0x3b, 10, PutAll }, - { "RMB2", 0x0000006, 0x5b, 10, PutAll }, - { "RMB3", 0x0000006, 0x7b, 10, PutAll }, - { "RMB4", 0x0000006, 0x9b, 10, PutAll }, - { "RMB5", 0x0000006, 0xbb, 10, PutAll }, - { "RMB6", 0x0000006, 0xdb, 10, PutAll }, - { "RMB7", 0x0000006, 0xfb, 10, PutAll }, - { "ROL", 0x000006F, 0x22, 1, PutAll }, - { "ROR", 0x000006F, 0x62, 1, PutAll }, - { "RRF", 0x0000004, 0x82, 6, PutAll }, - { "RTI", 0x0000001, 0x40, 0, PutAll }, - { "RTS", 0x0000001, 0x60, 0, PutAll }, - { "SBC", 0x080A26C, 0xe0, 0, PutAll }, - { "SEB0", 0x0000006, 0x0b, 10, PutAll }, - { "SEB1", 0x0000006, 0x2b, 10, PutAll }, - { "SEB2", 0x0000006, 0x4b, 10, PutAll }, - { "SEB3", 0x0000006, 0x6b, 10, PutAll }, - { "SEB4", 0x0000006, 0x8b, 10, PutAll }, - { "SEB5", 0x0000006, 0xab, 10, PutAll }, - { "SEB6", 0x0000006, 0xcb, 10, PutAll }, - { "SEB7", 0x0000006, 0xeb, 10, PutAll }, - { "SEC", 0x0000001, 0x38, 0, PutAll }, - { "SED", 0x0000001, 0xf8, 0, PutAll }, - { "SEI", 0x0000001, 0x78, 0, PutAll }, - { "SET", 0x0000001, 0x32, 0, PutAll }, - { "SLW", 0x0000001, 0xC2, 0, PutAll }, - { "STA", 0x000A26C, 0x80, 0, PutAll }, - { "STP", 0x0000001, 0x42, 0, PutAll }, - { "STX", 0x000010c, 0x82, 1, PutAll }, - { "STY", 0x000002c, 0x80, 1, PutAll }, - { "TAX", 0x0000001, 0xaa, 0, PutAll }, - { "TAY", 0x0000001, 0xa8, 0, PutAll }, - { "TST", 0x0000004, 0x64, 0, PutAll }, - { "TSX", 0x0000001, 0xba, 0, PutAll }, - { "TXA", 0x0000001, 0x8a, 0, PutAll }, - { "TXS", 0x0000001, 0x9a, 0, PutAll }, - { "TYA", 0x0000001, 0x98, 0, PutAll } + { "LDX", 0x0080030C, 0xa2, 1, PutAll }, + { "LDY", 0x0080006C, 0xa0, 1, PutAll }, + { "LSR", 0x0000006F, 0x42, 1, PutAll }, + { "NOP", 0x00000001, 0xea, 0, PutAll }, + { "ORA", 0x0080A26C, 0x00, 0, PutAll }, + { "PHA", 0x00000001, 0x48, 0, PutAll }, + { "PHP", 0x00000001, 0x08, 0, PutAll }, + { "PLA", 0x00000001, 0x68, 0, PutAll }, + { "PLP", 0x00000001, 0x28, 0, PutAll }, + { "RMB0", 0x00000006, 0x1b, 10, PutAll }, + { "RMB1", 0x00000006, 0x3b, 10, PutAll }, + { "RMB2", 0x00000006, 0x5b, 10, PutAll }, + { "RMB3", 0x00000006, 0x7b, 10, PutAll }, + { "RMB4", 0x00000006, 0x9b, 10, PutAll }, + { "RMB5", 0x00000006, 0xbb, 10, PutAll }, + { "RMB6", 0x00000006, 0xdb, 10, PutAll }, + { "RMB7", 0x00000006, 0xfb, 10, PutAll }, + { "ROL", 0x0000006F, 0x22, 1, PutAll }, + { "ROR", 0x0000006F, 0x62, 1, PutAll }, + { "RRF", 0x00000004, 0x82, 6, PutAll }, + { "RTI", 0x00000001, 0x40, 0, PutAll }, + { "RTS", 0x00000001, 0x60, 0, PutAll }, + { "SBC", 0x0080A26C, 0xe0, 0, PutAll }, + { "SEB0", 0x00000006, 0x0b, 10, PutAll }, + { "SEB1", 0x00000006, 0x2b, 10, PutAll }, + { "SEB2", 0x00000006, 0x4b, 10, PutAll }, + { "SEB3", 0x00000006, 0x6b, 10, PutAll }, + { "SEB4", 0x00000006, 0x8b, 10, PutAll }, + { "SEB5", 0x00000006, 0xab, 10, PutAll }, + { "SEB6", 0x00000006, 0xcb, 10, PutAll }, + { "SEB7", 0x00000006, 0xeb, 10, PutAll }, + { "SEC", 0x00000001, 0x38, 0, PutAll }, + { "SED", 0x00000001, 0xf8, 0, PutAll }, + { "SEI", 0x00000001, 0x78, 0, PutAll }, + { "SET", 0x00000001, 0x32, 0, PutAll }, + { "SLW", 0x00000001, 0xC2, 0, PutAll }, + { "STA", 0x0000A26C, 0x80, 0, PutAll }, + { "STP", 0x00000001, 0x42, 0, PutAll }, + { "STX", 0x0000010c, 0x82, 1, PutAll }, + { "STY", 0x0000002c, 0x80, 1, PutAll }, + { "TAX", 0x00000001, 0xaa, 0, PutAll }, + { "TAY", 0x00000001, 0xa8, 0, PutAll }, + { "TST", 0x00000004, 0x64, 1, PutAll }, + { "TSX", 0x00000001, 0xba, 0, PutAll }, + { "TXA", 0x00000001, 0x8a, 0, PutAll }, + { "TXS", 0x00000001, 0x9a, 0, PutAll }, + { "TYA", 0x00000001, 0x98, 0, PutAll } /* END SORTED.SH */ } }; @@ -1197,43 +1205,43 @@ static unsigned char EATab[14][AM65I_COUNT] = { 0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 1 */ + { /* Table 1 (rol, ror, stx, sty) */ 0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00, 0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 }, - { /* Table 2 */ + { /* Table 2 (bit) */ 0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 3 */ + { /* Table 3 (dec, dea) */ 0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 4 */ + { /* Table 4 (inc) */ 0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 5 */ + { /* Table 5 (stz) */ 0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 6 */ + { /* Table 6 (jmp) */ 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00 }, - { /* Table 7 (Subroutine opcodes) */ + { /* Table 7 (Subroutine opcodes) (jsr) */ 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1245,7 +1253,7 @@ static unsigned char EATab[14][AM65I_COUNT] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 9 */ + { /* Table 9 (dew, inw) */ 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1644,7 +1652,7 @@ static void PutBitBranch_m740 (const InsDesc* Ins) /* Accu */ Emit0 (A.Opcode); ConsumeComma (); - EmitSigned (GenBranchExpr (1), 1); + EmitSigned (GenBranchExpr (2), 1); } else if (A.AddrModeSet == 0x10000000) { A.Opcode += 0x04; /* Zeropage */ @@ -1870,6 +1878,59 @@ static void PutJSR816 (const InsDesc* Ins) } +static void PutJSR_m740 (const InsDesc* Ins) +/* Handle a JSR instruction for m740 */ +{ + EffAddr A; + + /* Evaluate the addressing mode used */ + GetEA (&A); + + /* From the possible addressing modes, remove the ones that are invalid + ** for this instruction or CPU. + */ + A.AddrModeSet &= Ins->AddrMode; + + /* Check if we have any adressing modes left */ + if (A.AddrModeSet == 0) { + Error ("Illegal addressing mode"); + return; + } + A.AddrMode = BitFind (A.AddrModeSet); + A.AddrModeBit = (0x01UL << A.AddrMode); + + /* Build the opcode */ + /* A.Opcode = Ins->BaseCode | EATab[Ins->ExtCode][A.AddrMode] | A.Reg; */ + A.Opcode = Ins->BaseCode; + + switch (A.AddrMode) { + case AM65I_DIR_IND: + A.Opcode = 0x02; + Emit1 (A.Opcode, A.Expr); + break; + case AM65I_ABS: + /* If we have an expression and it's const, get it's value */ + if (A.Expr) { + long Val = -1; + if (IsConstExpr (A.Expr, &Val)) { + if ((Val & 0xff00) == 0xff00) { + /* direct page */ + A.Opcode = 0x22; + Emit0 (A.Opcode); + EmitByte(GenByteExpr(A.Expr)); + return; + } + } + } + A.Opcode = 0x20; + Emit2 (A.Opcode, A.Expr); + break; + default: + Internal ("Invalid Opcode 0x%02x", A.Opcode); + } + +} + static void PutRTS (const InsDesc* Ins attribute ((unused))) /* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if diff --git a/src/ca65/instr.h b/src/ca65/instr.h index fff5a0f34..e31ae0734 100644 --- a/src/ca65/instr.h +++ b/src/ca65/instr.h @@ -68,8 +68,8 @@ #define AM65_ABS_LONG_X 0x00000080UL /* -- */ #define AM65_DIR_Y 0x00000100UL /* ZP, Y */ #define AM65_ABS_Y 0x00000200UL /* ABS, Y */ -#define AM65_DIR_IND 0x00000400UL /* ZP, IND */ -#define AM65_ABS_IND 0x00000800UL /* IND */ +#define AM65_DIR_IND 0x00000400UL /* (ZP IND) */ +#define AM65_ABS_IND 0x00000800UL /* (IND) */ #define AM65_DIR_IND_LONG 0x00001000UL /* -- */ #define AM65_DIR_IND_Y 0x00002000UL /* IND, Y */ #define AM65_DIR_IND_LONG_Y 0x00004000UL /* -- */ @@ -87,40 +87,55 @@ #define AM65_ABS_IND_LONG 0x04000000UL /* -- */ #define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */ #define AM65_ZP_REL 0x10000000UL /* ZP, REL (m740) */ +#define AM65_SPECIAL_PAGE 0x20000000UL /* $FFxx (m740) */ /* Bitmask for all ZP operations that have correspondent ABS ops */ -/* $8524 */ #define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND) - /*$4 $20 $100 $400 $8000 */ /* Bitmask for all ABS operations that have correspondent FAR ops */ -/* $48 */ #define AM65_SET_ABS (AM65_ABS | AM65_ABS_X) -/* $8 $40 */ /* Bitmask for all ZP operations */ -/* $8524 */ #define AM65_ALL_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND) - /*$4 $20 $100 $400 $8000 */ /* Bitmask for all ABS operations */ -/* $10a48 */ #define AM65_ALL_ABS (AM65_ABS | AM65_ABS_X | AM65_ABS_Y | AM65_ABS_IND | AM65_ABS_X_IND) -/* $8 $40 $200 $800 $10000 */ /* Bitmask for all FAR operations */ -/* $90 */ #define AM65_ALL_FAR (AM65_ABS_LONG | AM65_ABS_LONG_X) - /* $10 $80 */ - /* Bitmask for all immediate operations */ -/* $8e00 000 */ #define AM65_ALL_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD) -/* $200000 $400000 $800000 $8000000 */ + /* Bit numbers and count */ -#define AM65I_IMM_ACCU 21 -#define AM65I_IMM_INDEX 22 -#define AM65I_IMM_IMPLICIT 23 -#define AM65I_IMM_IMPLICIT_WORD 27 -#define AM65I_COUNT 28 +#define AM65I_IMPLICIT 0 +#define AM65I_ACCU 1 +#define AM65I_DIR 2 +#define AM65I_ABS 3 +#define AM65I_ABS_LONG 4 +#define AM65I_DIR_X 5 +#define AM65I_ABS_X 6 +#define AM65I_ABS_LONG_X 7 +#define AM65I_DIR_Y 8 +#define AM65I_ABS_Y 9 +#define AM65I_DIR_IND 10 +#define AM65I_ABS_IND 11 +#define AM65I_DIR_IND_LONG 12 +#define AM65I_DIR_IND_Y 13 +#define AM65I_DIR_IND_LONG_Y 14 +#define AM65I_DIR_X_IND 15 +#define AM65I_ABS_X_IND 16 +#define AM65I_REL 17 +#define AM65I_REL_LONG 18 +#define AM65I_STACK_REL 19 +#define AM65I_STACK_REL_IND_Y 20 +#define AM65I_IMM_ACCU 21 +#define AM65I_IMM_INDEX 22 +#define AM65I_IMM_IMPLICIT 23 +#define AM65I_BLOCKMOVE 24 +#define AM65I_BLOCKXFER 25 +#define AM65I_ABS_IND_LONG 26 +#define AM65I_IMM_IMPLICIT_WORD 27 +#define AM65I_ZP_REL 28 +#define AM65I_SPECIAL_PAGE 29 +#define AM65I_COUNT 30 diff --git a/src/da65/handler.c b/src/da65/handler.c index 356e84429..4f35fbaa3 100644 --- a/src/da65/handler.c +++ b/src/da65/handler.c @@ -795,14 +795,14 @@ void OH_JmpDirectIndirect (const OpcDesc* D) void OH_SpecialPage (const OpcDesc* D) { - /* Get the operand */ - unsigned Addr = 0xFF00 + GetCodeByte (PC+1); + /* Get the operand */ + unsigned Addr = 0xFF00 + GetCodeByte (PC+1); - /* Generate a label in pass 1 */ - GenerateLabel (D->Flags, Addr); + /* Generate a label in pass 1 */ + GenerateLabel (D->Flags, Addr); - /* OneLine (D, "$FF%02X", (CodeByte (PC+1)); */ - OneLine (D, "%s", GetAddrArg (D->Flags, Addr)); + /* OneLine (D, "$FF%02X", (CodeByte (PC+1)); */ + OneLine (D, "%s", GetAddrArg (D->Flags, Addr)); } diff --git a/src/da65/opcm740.c b/src/da65/opcm740.c index 676bf4dd4..6d12a7d37 100644 --- a/src/da65/opcm740.c +++ b/src/da65/opcm740.c @@ -44,7 +44,8 @@ /* Data */ /*****************************************************************************/ - +/* CAUTION: in the pdf $1a is dec, and $3a is inc - if that is really the case, + * the table below should be fixed and this notice removed */ /* Descriptions for all opcodes */ const OpcDesc OpcTable_M740[256] = { @@ -74,7 +75,7 @@ const OpcDesc OpcTable_M740[256] = { { "bbc0", 3, flUseLabel, OH_BitBranch_m740 }, /* $17 */ { "clc", 1, flNone, OH_Implicit }, /* $18 */ { "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */ - { "dec", 1, flNone, OH_Accumulator }, /* $1a */ + { "inc", 1, flNone, OH_Accumulator }, /* $1a */ { "clb0", 1, flNone, OH_AccumulatorBit }, /* $1b */ { "", 1, flIllegal, OH_Illegal }, /* $1c */ { "ora", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1d */ @@ -106,7 +107,7 @@ const OpcDesc OpcTable_M740[256] = { { "bbc1", 3, flUseLabel, OH_BitBranch_m740 }, /* $37 */ { "sec", 1, flNone, OH_Implicit }, /* $38 */ { "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */ - { "inc", 1, flNone, OH_Accumulator }, /* $3a */ + { "dec", 1, flNone, OH_Accumulator }, /* $3a */ { "clb1", 1, flNone, OH_AccumulatorBit }, /* $3b */ { "ldm", 3, flLabel, OH_DirectImmediate }, /* $3c */ { "and", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3d */ diff --git a/test/asm/opcodes/m740-opcodes.ref b/test/asm/opcodes/m740-opcodes.ref new file mode 100644 index 0000000000000000000000000000000000000000..b3cffc9b6c66b8de4f1cdec2e9ae8304a0b02588 GIT binary patch literal 768 zcmV~$0{|cd006OYdD*sY+qP}n{A}B{ZQHhO+qDg(fi;K*RT@l#YX}Xgp)|CH5e=*1 zG`vR8h#E;FYZQ&D(KNco(3l!aV{06ZtMN3xCeVbMNE2%kO{&Q>xu(#Rno3h^8cnO| zG`(ifjG9R^YZlF_*)+T6(43k}b88;WtNAp)7SMuPNDFHbEvm(|xR%h8T1rc687-^j zw7gc(idso4YZa}k)wH_S(3)CHYik{?tM#StZK}<*xwg=j+Dcn%8*QuY zw7quFj@n5(YZvXR-L$**(4N{$dut!kOT#vvju3(YZQL=j#GpsEc&5F43jBOqc5lU8$>dwXV^% zx=z>Y2HmKebhB>Jt-4LO>ki$iyL7ki(Y?A)_v-;YsE72h9?_$EOpogcJ*lVkw4Twk zdQQ*l1-+=3^s-*jt9nhZ>kYlBxAeB&(Ytz2@9P77sE_oqKGCQ8OrPrueW|bXwZ74} h`cB{L2mPp@^s|1^ulh~D>ks{@zx22M(ZBjn{{s(bkAVOH literal 0 HcmV?d00001 diff --git a/test/asm/opcodes/m740-opcodes.s b/test/asm/opcodes/m740-opcodes.s index df6d71488..e4f8562cc 100644 --- a/test/asm/opcodes/m740-opcodes.s +++ b/test/asm/opcodes/m740-opcodes.s @@ -1,260 +1,565 @@ -.setcpu "65C02" -; copy of 65c02, comments note changes to the m740 according to -; http://documentation.renesas.com/doc/products/mpumcu/rej09b0322_740sm.pdf +; da65 V2.19 - Git 89651fd8b +; Created: 2025-06-16 20:10:42 +; Input file: testfile +; Page: 1 - brk - ora ($12,x) - .byte $02,$00,$00 ; jsr zp,ind - .byte $03,$00,$00 ; bbs 0,a - tsb $12 ; .byte $04 - ora $12 - asl $12 - rmb0 $12 ; bbs 0,zp - php - ora #$12 - asl a - .byte $0B,$00,$00 ; seb 0,a - tsb $3456 ; .byte $0c - ora $3456 - asl $3456 - bbr0 $12,*+122 ; seb 0,zp - bpl *+122 - ora ($12),y - ora ($12) ; clt - .byte $13,$00,$00 ; bbc 0,a - trb $12 ; .byte $14 - ora $12,x - asl $12,x - rmb1 $12 ; bbc 0,zp - clc - ora $3456,y - inc a - .byte $1B,$00,$00 ; clb 0,a - trb $3456 ; .byte $1c - ora $3456,x - asl $3456,x - bbr1 $12,*+122 ; clb 0,zp - jsr $3456 - and ($12,x) - .byte $22,$00,$00 ; jsr sp - .byte $23,$00,$00 ; bbs 1,a - bit $12 - and $12 - rol $12 - rmb2 $12 ; bbs 1,zp - plp - and #$12 - rol a - .byte $2B,$00,$00 ; seb 1,a - bit $3456 - and $3456 - rol $3456 - bbr2 $12,*+122 ; seb 1,zp - bmi *+122 - and ($12),y - and ($12) ; set - .byte $33,$00,$00 ; bbc 1,a - bit $12,x ; .byte $34 - and $12,x - rol $12,x - rmb3 $12 ; bbc 1,zp - sec - and $3456,y - dec a - .byte $3B,$00,$00 ; clb 1,a - bit $3456,x ; ldm zp - and $3456,x - rol $3456,x - bbr3 $12,*+122 ; clb 1,zp - rti - eor ($12,x) - .byte $42,$00,$00 ; stp - .byte $43,$00,$00 ; bbs 2,a - .byte $44,$00,$00 ; com zp - eor $12 - lsr $12 - rmb4 $12 ; bbs 2,zp - pha - eor #$12 - lsr a - .byte $4B,$00,$00 ; seb 2,a - jmp $3456 - eor $3456 - lsr $3456 - bbr4 $12,*+122 ; seb 2,zp - bvc *+122 - eor ($12),y - eor ($12) ; .byte $52 - .byte $53,$00,$00 ; bbc 2,a - .byte $54,$00,$00 - eor $12,x - lsr $12,x - rmb5 $12 ; bbc 2,zp - cli - eor $3456,y - phy - .byte $5B,$00,$00 ; clb 2,a - .byte $5C,$00,$00 - eor $3456,x - lsr $3456,x - bbr5 $12,*+122 ; clb 2,zp - rts - adc ($12,x) - .byte $62,$00,$00 ; mul zp,x - .byte $63,$00,$00 ; bbs 3,a - stz $12 ; tst zp - adc $12 - ror $12 - rmb6 $12 ; bbs 3,zp - pla - adc #$12 - ror a - .byte $6B,$00,$00 ; seb 3,a - jmp ($3456) - adc $3456 - ror $3456 - bbr6 $12,*+122 ; seb 3,zp - bvs *+122 - adc ($12),y - adc ($12) ; .byte $72 - .byte $73,$00,$00 ; bbc 3,a - stz $12,x ; .byte $74 - adc $12,x - ror $12,x - rmb7 $12 ; bbc 3,zp - sei - adc $3456,y - ply - .byte $7B,$00,$00 ; clb 3,a - jmp ($3456,x) ; .byte $7c - adc $3456,x - ror $3456,x - bbr7 $12,*+122 ; clb 3,zp - bra *+122 - sta ($12,x) - .byte $82,$00,$00 ; rrf zp - .byte $83,$00,$00 ; bbs 4,a - sty $12 - sta $12 - stx $12 - smb0 $12 ; bbs 4,zp - dey - bit #$12 - txa - .byte $8B,$00,$00 ; seb 4,a - sty $3456 - sta $3456 - stx $3456 - bbs0 $12,*+122 ; seb 4,zp - bcc *+122 - sta ($12),y - sta ($12) ; .byte $92 - .byte $93,$00,$00 ; bbc 4,a - sty $12,x - sta $12,x - stx $12,y - smb1 $12 ; bbc 4,zp - tya - sta $3456,y - txs - .byte $9B,$00,$00 ; clb 4,a - stz $3456 ; .byte $9c - sta $3456,x - stz $3456,x ; .byte $9e - bbs1 $12,*+122 ; clb 4,zp - ldy #$12 - lda ($12,x) - ldx #$12 - .byte $A3,$00,$00 ; bbs 5,a - ldy $12 - lda $12 - ldx $12 - smb2 $12 ; bbs 5,zp - tay - lda #$12 - tax - .byte $AB,$00,$00 ; seb 5,a - ldy $3456 - lda $3456 - ldx $3456 - bbs2 $12,*+122 ; seb 5,zp - bcs *+122 - lda ($12),y - lda ($12) ; .byte $b2 - .byte $B3,$00,$00 ; bbc 5,a - ldy $12,x - lda $12,x - ldx $12,y - smb3 $12 ; bbc 5,zp - clv - lda $3456,y - tsx - .byte $BB,$00,$00 ; clb 5,a - ldy $3456,x - lda $3456,x - ldx $3456,y - bbs3 $12,*+122 ; clb 5,zp - cpy #$12 - cmp ($12,x) - .byte $C2,$00,$00 ; wit - .byte $C3,$00,$00 ; bbs 6,a - cpy $12 - cmp $12 - dec $12 - smb4 $12 ; bbs 6,zp - iny - cmp #$12 - dex - .byte $CB,$00,$00 ; seb 6,a - cpy $3456 - cmp $3456 - dec $3456 - bbs4 $12,*+122 ; seb 6,zp - bne *+122 - cmp ($12),y - cmp ($12) ; .byte $d2 - .byte $D3,$00,$00 ; bbc 6,a - .byte $D4,$00,$00 - cmp $12,x - dec $12,x - smb5 $12 ; bbc 6,zp - cld - cmp $3456,y - phx - .byte $DB,$00,$00 ; clb 6,a - .byte $DC,$00,$00 - cmp $3456,x - dec $3456,x - bbs5 $12,*+122 ; clb 6,zp - cpx #$12 - sbc ($12,x) - .byte $E2,$00,$00 ; div zp,x - .byte $E3,$00,$00 ; bbs 7,a - cpx $12 - sbc $12 - inc $12 - smb6 $12 ; bbs 7,zp - inx - sbc #$12 - nop - .byte $EB,$00,$00 ; seb 7,a - cpx $3456 - sbc $3456 - inc $3456 - bbs6 $12,*+122 ; seb 7,zp - beq *+122 - sbc ($12),y - sbc ($12) ; .byte $f2 - .byte $F3,$00,$00 ; bbc 7,a - .byte $F4,$00,$00 - sbc $12,x - inc $12,x - smb7 $12 ; bbc 7,zp - sed - sbc $3456,y - plx - .byte $FB,$00,$00 ; clb 7,a - .byte $FC,$00,$00 - sbc $3456,x - inc $3456,x - bbs7 $12,*+122 ; clb 7,zp + + .setcpu "m740" + +L000C := $000C +L040C := $040C +LFF0C := $FF0C + brk + .byte $0C + .byte $04 + ora (L000C,x) + .byte $04 + jsr (L000C) + + .byte $04 + bbs0 a, L8018 + .byte $04 + .byte $04 + .byte $0C + .byte $04 + ora L000C + .byte $04 + asl L000C + .byte $04 + bbs0 L000C, L801C +L8018: php + .byte $0C + .byte $04 + .byte $09 +L801C: .byte $0C + .byte $04 + asl a + .byte $0C + .byte $04 + seb0 a + .byte $0C + .byte $04 + .byte $0C + .byte $0C + .byte $04 + ora L040C + asl L040C + seb0 L000C + .byte $04 + bpl L803E + .byte $04 + ora (L000C),y + .byte $04 + clt + .byte $0C + .byte $04 + bbc0 a, L8048 + .byte $04 + .byte $14 + .byte $0C +L803E: .byte $04 + ora L000C,x + .byte $04 + asl L000C,x + .byte $04 + bbc0 L000C, L804C +L8048: clc + .byte $0C + .byte $04 + .byte $19 +L804C: .byte $0C + .byte $04 + inc a + .byte $0C + .byte $04 + clb0 a + .byte $0C + .byte $04 + .byte $1C + .byte $0C + .byte $04 + ora L040C,x + asl L040C,x + clb0 L000C + .byte $04 + jsr L040C + and (L000C,x) + .byte $04 + jsr LFF0C + .byte $04 + bbs1 a, L8078 + .byte $04 + bit L000C + .byte $04 + and L000C + .byte $04 + rol L000C + .byte $04 + bbs1 L000C, L807C +L8078: plp + .byte $0C + .byte $04 + .byte $29 +L807C: .byte $0C + .byte $04 + rol a + .byte $0C + .byte $04 + seb1 a + .byte $0C + .byte $04 + bit L040C + and L040C + rol L040C + seb1 L000C + .byte $04 + bmi L809E + .byte $04 + and (L000C),y + .byte $04 + set + .byte $0C + .byte $04 + bbc1 a, L80A8 + .byte $04 + .byte $34 + .byte $0C +L809E: .byte $04 + and L000C,x + .byte $04 + rol L000C,x + .byte $04 + bbc1 L000C, L80AC +L80A8: sec + .byte $0C + .byte $04 + .byte $39 +L80AC: .byte $0C + .byte $04 + dec a + .byte $0C + .byte $04 + clb1 a + .byte $0C + .byte $04 + ldm L000C, #$04 + and L040C,x + rol L040C,x + clb1 L000C + .byte $04 + rti + + .byte $0C + .byte $04 + eor (L000C,x) + .byte $04 + stp + .byte $0C + .byte $04 + bbs2 a, L80D8 + .byte $04 + com L000C + .byte $04 + eor L000C + .byte $04 + lsr L000C + .byte $04 + bbs2 L000C, L80DC +L80D8: pha + .byte $0C + .byte $04 + .byte $49 +L80DC: .byte $0C + .byte $04 + lsr a + .byte $0C + .byte $04 + seb2 a + .byte $0C + .byte $04 + jmp L040C + + eor L040C + lsr L040C + seb2 L000C + .byte $04 + bvc L80FE + .byte $04 + eor (L000C),y + .byte $04 + .byte $52 + .byte $0C + .byte $04 + bbc2 a, L8108 + .byte $04 + .byte $54 + .byte $0C +L80FE: .byte $04 + eor L000C,x + .byte $04 + lsr L000C,x + .byte $04 + bbc2 L000C, L810C +L8108: cli + .byte $0C + .byte $04 + .byte $59 +L810C: .byte $0C + .byte $04 + .byte $5A + .byte $0C + .byte $04 + clb2 a + .byte $0C + .byte $04 + .byte $5C + .byte $0C + .byte $04 + eor L040C,x + lsr L040C,x + clb2 L000C + .byte $04 + rts + + .byte $0C + .byte $04 + adc (L000C,x) + .byte $04 + .byte $62 + .byte $0C + .byte $04 + bbs3 a, L8138 + .byte $04 + tst L000C + .byte $04 + adc L000C + .byte $04 + ror L000C + .byte $04 + bbs3 L000C, L813C +L8138: pla + .byte $0C + .byte $04 + .byte $69 +L813C: .byte $0C + .byte $04 + ror a + .byte $0C + .byte $04 + seb3 a + .byte $0C + .byte $04 + jmp (L040C) + + adc L040C + ror L040C + seb3 L000C + .byte $04 + bvs L815E + .byte $04 + adc (L000C),y + .byte $04 + .byte $72 + .byte $0C + .byte $04 + bbc3 a, L8168 + .byte $04 + .byte $74 + .byte $0C +L815E: .byte $04 + adc L000C,x + .byte $04 + ror L000C,x + .byte $04 + bbc3 L000C, L816C +L8168: sei + .byte $0C + .byte $04 + .byte $79 +L816C: .byte $0C + .byte $04 + .byte $7A + .byte $0C + .byte $04 + clb3 a + .byte $0C + .byte $04 + .byte $7C + .byte $0C + .byte $04 + adc L040C,x + ror L040C,x + clb3 L000C + .byte $04 + bra L818E + .byte $04 + sta (L000C,x) + .byte $04 + rrf L000C + .byte $04 + bbs4 a, L8198 + .byte $04 + sty L000C +L818E: .byte $04 + sta L000C + .byte $04 + stx L000C + .byte $04 + bbs4 L000C, L819C +L8198: dey + .byte $0C + .byte $04 + .byte $89 +L819C: .byte $0C + .byte $04 + txa + .byte $0C + .byte $04 + seb4 a + .byte $0C + .byte $04 + sty L040C + sta L040C + stx L040C + seb4 L000C + .byte $04 + bcc L81BE + .byte $04 + sta (L000C),y + .byte $04 + .byte $92 + .byte $0C + .byte $04 + bbc4 a, L81C8 + .byte $04 + sty L000C,x +L81BE: .byte $04 + sta L000C,x + .byte $04 + stx L000C,y + .byte $04 + bbc4 L000C, L81CC +L81C8: tya + .byte $0C + .byte $04 + .byte $99 +L81CC: .byte $0C + .byte $04 + txs + .byte $0C + .byte $04 + clb4 a + .byte $0C + .byte $04 + .byte $9C + .byte $0C + .byte $04 + sta L040C,x + .byte $9E + .byte $0C + .byte $04 + clb4 L000C + .byte $04 + ldy #$0C + .byte $04 + lda (L000C,x) + .byte $04 + ldx #$0C + .byte $04 + bbs5 a, L81F8 + .byte $04 + ldy L000C + .byte $04 + lda L000C + .byte $04 + ldx L000C + .byte $04 + bbs5 L000C, L81FC +L81F8: tay + .byte $0C + .byte $04 + .byte $A9 +L81FC: .byte $0C + .byte $04 + tax + .byte $0C + .byte $04 + seb5 a + .byte $0C + .byte $04 + ldy L040C + lda L040C + ldx L040C + seb5 L000C + .byte $04 + bcs L821E + .byte $04 + lda (L000C),y + .byte $04 + jmp (L000C) + + .byte $04 + bbc5 a, L8228 + .byte $04 + ldy L000C,x +L821E: .byte $04 + lda L000C,x + .byte $04 + ldx L000C,y + .byte $04 + bbc5 L000C, L822C +L8228: clv + .byte $0C + .byte $04 + .byte $B9 +L822C: .byte $0C + .byte $04 + tsx + .byte $0C + .byte $04 + clb5 a + .byte $0C + .byte $04 + ldy L040C,x + lda L040C,x + ldx L040C,y + clb5 L000C + .byte $04 + cpy #$0C + .byte $04 + cmp (L000C,x) + .byte $04 + slw + .byte $0C + .byte $04 + bbs6 a, L8258 + .byte $04 + cpy L000C + .byte $04 + cmp L000C + .byte $04 + dec L000C + .byte $04 + bbs6 L000C, L825C +L8258: iny + .byte $0C + .byte $04 + .byte $C9 +L825C: .byte $0C + .byte $04 + dex + .byte $0C + .byte $04 + seb6 a + .byte $0C + .byte $04 + cpy L040C + cmp L040C + dec L040C + seb6 L000C + .byte $04 + bne L827E + .byte $04 + cmp (L000C),y + .byte $04 + .byte $D2 + .byte $0C + .byte $04 + bbc6 a, L8288 + .byte $04 + .byte $D4 + .byte $0C +L827E: .byte $04 + cmp L000C,x + .byte $04 + dec L000C,x + .byte $04 + bbc6 L000C, L828C +L8288: cld + .byte $0C + .byte $04 + .byte $D9 +L828C: .byte $0C + .byte $04 + .byte $DA + .byte $0C + .byte $04 + clb6 a + .byte $0C + .byte $04 + .byte $DC + .byte $0C + .byte $04 + cmp L040C,x + dec L040C,x + clb6 L000C + .byte $04 + cpx #$0C + .byte $04 + sbc (L000C,x) + .byte $04 + fst + .byte $0C + .byte $04 + bbs7 a, L82B8 + .byte $04 + cpx L000C + .byte $04 + sbc L000C + .byte $04 + inc L000C + .byte $04 + bbs7 L000C, L82BC +L82B8: inx + .byte $0C + .byte $04 + .byte $E9 +L82BC: .byte $0C + .byte $04 + nop + .byte $0C + .byte $04 + seb7 a + .byte $0C + .byte $04 + cpx L040C + sbc L040C + inc L040C + seb7 L000C + .byte $04 + beq L82DE + .byte $04 + sbc (L000C),y + .byte $04 + .byte $F2 + .byte $0C + .byte $04 + bbc7 a, L82E8 + .byte $04 + .byte $F4 + .byte $0C +L82DE: .byte $04 + sbc L000C,x + .byte $04 + inc L000C,x + .byte $04 + bbc7 L000C, L82EC +L82E8: sed + .byte $0C + .byte $04 + .byte $F9 +L82EC: .byte $0C + .byte $04 + .byte $FA + .byte $0C + .byte $04 + clb7 a + .byte $0C + .byte $04 + .byte $FC + .byte $0C + .byte $04 + sbc L040C,x + inc L040C,x + clb7 L000C + .byte $04