Replaced builtin linker configs with ordinary .cfg files.
The benefits are: - Independency of ld65 build from perl - More transparent behaviour
This commit is contained in:
62
cfg/nes.cfg
Normal file
62
cfg/nes.cfg
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@@ -0,0 +1,62 @@
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SYMBOLS {
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__STACKSIZE__: type = weak, value = $0300; # 3 pages stack
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}
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MEMORY {
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ZP: file = "", start = $0002, size = $001A, type = rw, define = yes;
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# INES Cartridge Header
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HEADER: file = %O, start = $0000, size = $0010, fill = yes;
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# 2 16K ROM Banks
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# - startup
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# - code
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# - rodata
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# - data (load)
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ROM0: file = %O, start = $8000, size = $7FF4, fill = yes, define = yes;
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# Hardware Vectors at End of 2nd 8K ROM
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ROMV: file = %O, start = $FFF6, size = $000C, fill = yes;
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# 1 8k CHR Bank
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ROM2: file = %O, start = $0000, size = $2000, fill = yes;
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# standard 2k SRAM (-zeropage)
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# $0100-$0200 cpu stack
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# $0200-$0500 3 pages for ppu memory write buffer
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# $0500-$0800 3 pages for cc65 parameter stack
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SRAM: file = "", start = $0500, size = __STACKSIZE__, define = yes;
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# additional 8K SRAM Bank
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# - data (run)
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# - bss
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# - heap
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RAM: file = "", start = $6000, size = $2000, define = yes;
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}
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SEGMENTS {
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HEADER: load = HEADER, type = ro;
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STARTUP: load = ROM0, type = ro, define = yes;
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LOWCODE: load = ROM0, type = ro, optional = yes;
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INIT: load = ROM0, type = ro, define = yes, optional = yes;
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CODE: load = ROM0, type = ro, define = yes;
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RODATA: load = ROM0, type = ro, define = yes;
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DATA: load = ROM0, run = RAM, type = rw, define = yes;
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VECTORS: load = ROMV, type = rw;
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CHARS: load = ROM2, type = rw;
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BSS: load = RAM, type = bss, define = yes;
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ZEROPAGE: load = ZP, type = zp;
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}
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FEATURES {
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CONDES: type = constructor,
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label = __CONSTRUCTOR_TABLE__,
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count = __CONSTRUCTOR_COUNT__,
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segment = INIT;
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CONDES: type = destructor,
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label = __DESTRUCTOR_TABLE__,
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count = __DESTRUCTOR_COUNT__,
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segment = RODATA;
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CONDES: type = interruptor,
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label = __INTERRUPTOR_TABLE__,
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count = __INTERRUPTOR_COUNT__,
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segment = RODATA,
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import = __CALLIRQ__;
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}
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