cleanup/fix test for 65816
This commit is contained in:
mrdudz
@@ -357,7 +357,6 @@ LABEL:
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.endscope
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.endscope
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.endif
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.endif
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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; The 65sc02 is the original CMOS re-design of the 6502.
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; The 65sc02 is the original CMOS re-design of the 6502.
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;
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;
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@@ -426,27 +425,7 @@ LABEL:
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.endif
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.endif
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; Rockwell Datasheet "R65C02, R65C102, R65C112 R65C00 Microprocessors (CPU)" 1987,rev6:
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;
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; The 8-bit R65C00 microprocessor family of devices are produced using CMOS [...]
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; technology which provides advanced [...] performance speed and [...] over their
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; NMOS counterparts, the R6500 family of microprocessor devices. [...]
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; The CMOS family ... has been designed with many enhancements over the R6502
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; NMOS device [...]
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;
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; The R65C02 is a superset of the 65C02. It adds bit manipulation instructions:
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; The R65C02 is a superset of the 65C02. It adds bit manipulation instructions:
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;
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; smbB zp set bit in zp location
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; rmbB zp reset bit in zp location
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; bbsB zp, rel8 branch if bit is set in zp location
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; bbrB zp, rel8 branch if bit is reset in zp location
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;
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; 12 new instructions for a total of 68
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; 59 new op ocdes, for a total of 210
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; two new addressing modes
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; seven software/operational enhancements
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; two hardware enhancements
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.if (.cpu .bitand CPU_ISET_65C02)
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.if (.cpu .bitand CPU_ISET_65C02)
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; R65C02 instruction set adds some extra legal instructions to 65C02
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; R65C02 instruction set adds some extra legal instructions to 65C02
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@@ -488,10 +467,6 @@ LABEL3:
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; The W65C02 is a superset of the R65C02. It only adds two instructions:
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; The W65C02 is a superset of the R65C02. It only adds two instructions:
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;
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; $cb wai wait for interrupt
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; $db stp wait for reset
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.if (.cpu .bitand CPU_ISET_W65C02)
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.if (.cpu .bitand CPU_ISET_W65C02)
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wai ; $cb
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wai ; $cb
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stp ; $db
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stp ; $db
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@@ -499,68 +474,9 @@ LABEL3:
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; The 65CE02 is another superset of the R65C02. It has several improvements:
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; The 65CE02 is another superset of the R65C02. It has several improvements:
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;
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; $02 cle clear stack extend disable
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; $03 see set stack extend disable
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; $0b tsy transfer stack_ptr_high to Y
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; $12 ora (zp), z
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; $13 lbpl rel16
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; $1b inz increment Z
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; $22 jsr (abs16)
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; $23 jsr (abs16, x)
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; $2b tys transfer Y to stack_ptr_high
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; $32 and (zp), z
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; $33 lbmi rel16
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; $3b dez decrement Z
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; $42 neg negate A
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; $43 asr
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; $44 asr zp
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; $4b taz transfer A to Z
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; $52 eor (zp), z
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; $53 lbvc rel16
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; $54 asr zp, x
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; $5b tab
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; $5c aug "4-byte NOP reserved for future expansion"
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; $62 rtn #imm8
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; $63 lbsr rel16 relative jsr, "branch to subroutine"
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; $64 stz zp store Z
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; $6b tza transfer Z to A
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; $72 adc (zp), z
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; $73 lbvs rel16
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; $74 stz zp, x store Z
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; $7b tba
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; $82 sta (off8, s), y
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; $83 lbra rel16 relative jmp
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; $8b sty abs16, x
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; $92 sta (zp), z
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; $93 lbcc rel16
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; $9b stx abs16, y
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; $9c stz abs16 store Z
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; $9e stz abs16, x store Z
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; $a3 ldz #imm8
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; $ab ldz abs16
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; $b2 lda (zp), z
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; $b3 lbcs rel16
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; $bb ldz abs16, x
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; $c2 cpz #imm8
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; $c3 dew zp
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; $cb asw abs16
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; $d2 cmp (zp), z
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; $d3 lbne rel16
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; $d4 cpz zp
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; $db phz push Z
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; $dc cpz abs16
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; $e2 lda (off8, s), y
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; $e3 inw zp
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; $eb row abs16
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; $f2 sbc (zp), z
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; $f3 lbeq rel16
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; $f4 phw #imm16
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; $fb plz pull Z
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; $fc phw abs16
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.if (.cpu .bitand CPU_ISET_65CE02)
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.if (.cpu .bitand CPU_ISET_65CE02)
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.scope
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.scope
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; 65CE02 adds the following:
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; 65CE02 adds the following:
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cle ; $02
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cle ; $02
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see ; $03
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see ; $03
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@@ -879,3 +795,178 @@ LABEL:
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.endscope
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.endscope
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.endif
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.endif
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.if (.cpu .bitand CPU_ISET_65816)
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.smart - ; Stop being smart
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.A8 ; akku 8 bit
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.I8 ; index registers 8 bit
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.scope
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cop $12 ; $02 coprocessor operation
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ora $12, s ; $03
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ora [$12] ; $07
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phd ; $0b push direct page register
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ora $123456 ; $0f
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ora ($12, s), y ; $13
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ora [$12], y ; $17
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tcs ; $1b transfer C to stack pointer
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ora $123456, x ; $1f
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jsl $123456 ; $22
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and $12, s ; $23
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and [$12] ; $27
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pld ; $2b pull direct page register
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and $123456 ; $2f
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and ($12, s), y ; $33
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and [$12], y ; $37
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tsc ; $3b transfer stack pointer to C
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and $123456, x ; $3f
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wdm $12 ; $42 (reserved for future expansion)
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eor $12, s ; $43
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mvp $1234, $5678 ; $44
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eor [$12] ; $47
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phk ; $4b push program bank register
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eor $123456 ; $4f
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eor ($12, s), y ; $53
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mvn $1234, $5678 ; $54
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eor [$12], y ; $57
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tcd ; $5b transfer C to direct page register
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jml $123456 ; $5c
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eor $123456, x ; $5f
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per LABEL ; $62 push effective relative address
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adc $12, s ; $63
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adc [$12] ; $67
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rtl ; $6b return long (fetches 24-bit address from stack)
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adc $123456 ; $6f
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adc ($12, s), y ; $73
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adc [$12], y ; $77
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tdc ; $7b transfer direct page register to C
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adc $123456, x ; $7f
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LABEL:
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brl LABEL ; $82 branch long (16-bit offset)
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sta $12, s ; $83
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sta [$12] ; $87
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phb ; $8b push data bank register
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sta $123456 ; $8f
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sta ($12, s), y ; $93
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sta [$12], y ; $97
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txy ; $9b transfer X to Y
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sta $123456, x ; $9f
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lda $12, s ; $a3
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lda [$12] ; $a7
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plb ; $ab pull data bank register
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lda $123456 ; $af
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lda ($12, s), y ; $b3
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lda [$12], y ; $b7
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tyx ; $bb transfer Y to X
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lda $123456, x ; $bf
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rep #$12 ; $c2 clear bits in status register
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cmp $12, s ; $c3
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cmp [$12] ; $c7
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wai ; $cb wait for interrupt
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cmp $123456 ; $cf
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cmp ($12, s), y ; $d3
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pei ($12) ; $d4 push effective indirect address
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cmp [$12], y ; $d7
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stp ; $db wait for reset
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jmp [$1234] ; $dc
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cmp $123456, x ; $df
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sep #$12 ; $e2 set bits in status register
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sbc $12, s ; $e3
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sbc [$12] ; $e7
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xba ; $eb exchange high and low bytes of accumulator
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sbc $123456 ; $ef
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sbc ($12, s), y ; $f3
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pea $1234 ; $f4 push effective absolute address
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sbc [$12], y ; $f7
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xce ; $fb exchange Carry and Emulation bits
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jsr ($1234, x) ; $fc
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sbc $123456, x ; $ff
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.endscope
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.A16 ; akku 16 bit
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.I16 ; index registers 16 bit
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.scope
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cop $12 ; $02 coprocessor operation
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ora $12, s ; $03
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ora [$12] ; $07
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phd ; $0b push direct page register
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ora $123456 ; $0f
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ora ($12, s), y ; $13
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ora [$12], y ; $17
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tcs ; $1b transfer C to stack pointer
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ora $123456, x ; $1f
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jsl $123456 ; $22
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and $12, s ; $23
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and [$12] ; $27
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pld ; $2b pull direct page register
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and $123456 ; $2f
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and ($12, s), y ; $33
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and [$12], y ; $37
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tsc ; $3b transfer stack pointer to C
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and $123456, x ; $3f
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wdm $12 ; $42 (reserved for future expansion)
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eor $12, s ; $43
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mvp $1234, $5678 ; $44
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eor [$12] ; $47
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phk ; $4b push program bank register
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eor $123456 ; $4f
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eor ($12, s), y ; $53
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mvn $1234, $5678 ; $54
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eor [$12], y ; $57
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tcd ; $5b transfer C to direct page register
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jml $123456 ; $5c
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eor $123456, x ; $5f
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per LABEL ; $62 push effective relative address
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adc $12, s ; $63
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adc [$12] ; $67
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rtl ; $6b return long (fetches 24-bit address from stack)
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adc $123456 ; $6f
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adc ($12, s), y ; $73
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adc [$12], y ; $77
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tdc ; $7b transfer direct page register to C
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adc $123456, x ; $7f
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LABEL:
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brl LABEL ; $82 branch long (16-bit offset)
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sta $12, s ; $83
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sta [$12] ; $87
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phb ; $8b push data bank register
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sta $123456 ; $8f
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sta ($12, s), y ; $93
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sta [$12], y ; $97
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txy ; $9b transfer X to Y
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sta $123456, x ; $9f
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lda $12, s ; $a3
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lda [$12] ; $a7
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plb ; $ab pull data bank register
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lda $123456 ; $af
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lda ($12, s), y ; $b3
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lda [$12], y ; $b7
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tyx ; $bb transfer Y to X
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lda $123456, x ; $bf
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rep #$12 ; $c2 clear bits in status register
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cmp $12, s ; $c3
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cmp [$12] ; $c7
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wai ; $cb wait for interrupt
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cmp $123456 ; $cf
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cmp ($12, s), y ; $d3
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pei ($12) ; $d4 push effective indirect address
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cmp [$12], y ; $d7
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stp ; $db wait for reset
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jmp [$1234] ; $dc
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cmp $123456, x ; $df
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sep #$12 ; $e2 set bits in status register
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sbc $12, s ; $e3
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sbc [$12] ; $e7
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xba ; $eb exchange high and low bytes of accumulator
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sbc $123456 ; $ef
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sbc ($12, s), y ; $f3
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pea $1234 ; $f4 push effective absolute address
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sbc [$12], y ; $f7
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xce ; $fb exchange Carry and Emulation bits
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jsr ($1234, x) ; $fc
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sbc $123456, x ; $ff
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.endscope
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.endif
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@@ -12,6 +12,11 @@
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lax #$ea
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lax #$ea
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.endif
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.endif
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.ifp6280
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sax
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cla
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.endif
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.ifpsc02
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.ifpsc02
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jmp ($1234,x)
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jmp ($1234,x)
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.endif
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.endif
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@@ -29,10 +34,6 @@
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ldz #$12
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ldz #$12
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.endif
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.endif
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.ifp816
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xba
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.endif
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.ifp4510
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.ifp4510
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taz
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taz
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.endif
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.endif
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@@ -45,15 +46,14 @@
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sac #$00
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sac #$00
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.endif
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.endif
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.ifp6280
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sax
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cla
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.endif
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.ifpm740
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.ifpm740
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jsr $ff12
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jsr $ff12
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.endif
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.endif
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.ifp816
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xba
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.endif
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; step 2: check for bitwise compatibility of instructions sets
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; step 2: check for bitwise compatibility of instructions sets
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; (made verbose for better reading with hexdump/hd(1))
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; (made verbose for better reading with hexdump/hd(1))
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@@ -115,10 +115,7 @@
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.endif
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.endif
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; FIXME: something with 65816 is quirky
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.include "allinst.inc"
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;.if (.not .cpu .bitand CPU_ISET_65816)
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.include "allinst.inc"
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;.endif
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; step 3: switch through all supported cpus to verify the pseudo-op is there
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; step 3: switch through all supported cpus to verify the pseudo-op is there
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Block a user