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Polishing the peripherals (and counter) interface.

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sidney
2024-12-19 03:48:15 +01:00
parent 8a7cd9c632
commit 5239d3a11b
5 changed files with 117 additions and 102 deletions
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123
src/sim65/peripherals.c
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@@ -40,8 +40,8 @@
/* The peripheral registers. */
PeripheralRegs PRegs;
/* The system-wide state of the peripherals */
Sim65Peripherals Peripherals;
@@ -51,46 +51,37 @@ PeripheralRegs PRegs;
static uint64_t get_uint64_wallclock_time(void)
{
struct timespec ts;
int result = clock_gettime(CLOCK_REALTIME, &ts);
if (result != 0)
{
// On failure, time will be set to the max value.
return 0xffffffffffffffff;
}
/* Return time since the 1-1-1970 epoch, in nanoseconds.
* Note that this time may be off by an integer number of seconds, as POSIX
* maintaines that all days are 86,400 seconds long, which is not true due to
* leap seconds.
*/
return ts.tv_sec * 1000000000 + ts.tv_nsec;
}
void PeripheralWriteByte (uint8_t Addr, uint8_t Val)
/* Write a byte to a memory location in the peripheral address aperture. */
void PeripheralsWriteByte (uint8_t Addr, uint8_t Val)
/* Write a byte to a memory location in the peripherals address aperture. */
{
switch (Addr) {
case PERIPHERALS_ADDRESS_OFFSET_LATCH: {
/* A write to the "latch" register performs a simultaneous latch of all registers */
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_LATCH: {
/* A write to the "latch" register performs a simultaneous latch of all registers. */
/* Latch the current wallclock time first. */
PRegs.latched_wallclock_time = get_uint64_wallclock_time();
struct timespec ts;
int result = clock_gettime(CLOCK_REALTIME, &ts);
if (result != 0) {
/* Unable to read time. Report max uint64 value for both fields. */
Peripherals.Counter.latched_wallclock_time = 0xffffffffffffffff;
Peripherals.Counter.latched_wallclock_time_split = 0xffffffffffffffff;
} else {
/* Number of nanoseconds since 1-1-1970. */
Peripherals.Counter.latched_wallclock_time = 1000000000u * ts.tv_sec + ts.tv_nsec;
/* High word is number of seconds, low word is number of nanoseconds. */
Peripherals.Counter.latched_wallclock_time_split = (ts.tv_sec << 32) | ts.tv_nsec;
}
/* Now latch all the cycles maintained by the processor. */
PRegs.latched_counter_clock_cycles = PRegs.counter_clock_cycles;
PRegs.latched_counter_instructions = PRegs.counter_instructions;
PRegs.latched_counter_irq_events = PRegs.counter_irq_events;
PRegs.latched_counter_nmi_events = PRegs.counter_nmi_events;
/* Latch the counters that reflect the state of the processor. */
Peripherals.Counter.latched_clock_cycles = Peripherals.Counter.clock_cycles;
Peripherals.Counter.latched_cpu_instructions = Peripherals.Counter.cpu_instructions;
Peripherals.Counter.latched_irq_events = Peripherals.Counter.irq_events;
Peripherals.Counter.latched_nmi_events = Peripherals.Counter.nmi_events;
break;
}
case PERIPHERALS_ADDRESS_OFFSET_SELECT: {
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_SELECT: {
/* Set the value of the visibility-selection register. */
PRegs.visible_latch_register = Val;
Peripherals.Counter.visible_latch_register = Val;
break;
}
default: {
@@ -101,33 +92,34 @@ void PeripheralWriteByte (uint8_t Addr, uint8_t Val)
uint8_t PeripheralReadByte (uint8_t Addr)
/* Read a byte from a memory location in the peripheral address aperture. */
uint8_t PeripheralsReadByte (uint8_t Addr)
/* Read a byte from a memory location in the peripherals address aperture. */
{
switch (Addr) {
case PERIPHERALS_ADDRESS_OFFSET_SELECT: {
return PRegs.visible_latch_register;
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_SELECT: {
return Peripherals.Counter.visible_latch_register;
}
case PERIPHERALS_ADDRESS_OFFSET_REG64 + 0:
case PERIPHERALS_ADDRESS_OFFSET_REG64 + 1:
case PERIPHERALS_ADDRESS_OFFSET_REG64 + 2:
case PERIPHERALS_ADDRESS_OFFSET_REG64 + 3:
case PERIPHERALS_ADDRESS_OFFSET_REG64 + 4:
case PERIPHERALS_ADDRESS_OFFSET_REG64 + 5:
case PERIPHERALS_ADDRESS_OFFSET_REG64 + 6:
case PERIPHERALS_ADDRESS_OFFSET_REG64 + 7: {
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE + 0:
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE + 1:
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE + 2:
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE + 3:
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE + 4:
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE + 5:
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE + 6:
case PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE + 7: {
/* Read from any of the eight counter bytes.
* The first byte is the 64 bit value's LSB, the seventh byte is its MSB.
*/
unsigned byte_select = Addr - PERIPHERALS_ADDRESS_OFFSET_REG64; /* 0 .. 7 */
unsigned byte_select = Addr - PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE; /* 0 .. 7 */
uint64_t value;
switch (PRegs.visible_latch_register) {
case PERIPHERALS_REG64_SELECT_CLOCKCYCLE_COUNTER: value = PRegs.latched_counter_clock_cycles; break;
case PERIPHERALS_REG64_SELECT_INSTRUCTION_COUNTER: value = PRegs.latched_counter_instructions; break;
case PERIPHERALS_REG64_SELECT_IRQ_COUNTER: value = PRegs.latched_counter_irq_events; break;
case PERIPHERALS_REG64_SELECT_NMI_COUNTER: value = PRegs.latched_counter_nmi_events; break;
case PERIPHERALS_REG64_SELECT_WALLCLOCK_TIME: value = PRegs.latched_wallclock_time; break;
default: value = 0; /* Reading from a non-supported register will yield 0. */
switch (Peripherals.Counter.visible_latch_register) {
case PERIPHERALS_COUNTER_SELECT_CLOCKCYCLE_COUNTER: value = Peripherals.Counter.latched_clock_cycles; break;
case PERIPHERALS_COUNTER_SELECT_INSTRUCTION_COUNTER: value = Peripherals.Counter.latched_cpu_instructions; break;
case PERIPHERALS_COUNTER_SELECT_IRQ_COUNTER: value = Peripherals.Counter.latched_irq_events; break;
case PERIPHERALS_COUNTER_SELECT_NMI_COUNTER: value = Peripherals.Counter.latched_nmi_events; break;
case PERIPHERALS_COUNTER_SELECT_WALLCLOCK_TIME: value = Peripherals.Counter.latched_wallclock_time; break;
case PERIPHERALS_COUNTER_SELECT_WALLCLOCK_TIME_SPLIT: value = Peripherals.Counter.latched_wallclock_time_split; break;
default: value = 0; /* Reading from a non-existent register will yield 0. */
}
/* Return the desired byte of the latched counter. 0==LSB, 7==MSB. */
return value >> (byte_select * 8);
@@ -144,16 +136,19 @@ uint8_t PeripheralReadByte (uint8_t Addr)
void PeripheralsInit (void)
/* Initialize the peripheral registers */
{
PRegs.counter_clock_cycles = 0;
PRegs.counter_instructions = 0;
PRegs.counter_irq_events = 0;
PRegs.counter_nmi_events = 0;
/* Initialize the COUNTER peripheral */
PRegs.latched_counter_clock_cycles = 0;
PRegs.latched_counter_instructions = 0;
PRegs.latched_counter_irq_events = 0;
PRegs.latched_counter_nmi_events = 0;
PRegs.latched_wallclock_time = 0;
Peripherals.Counter.clock_cycles = 0;
Peripherals.Counter.cpu_instructions = 0;
Peripherals.Counter.irq_events = 0;
Peripherals.Counter.nmi_events = 0;
PRegs.visible_latch_register = 0;
Peripherals.Counter.latched_clock_cycles = 0;
Peripherals.Counter.latched_cpu_instructions = 0;
Peripherals.Counter.latched_irq_events = 0;
Peripherals.Counter.latched_nmi_events = 0;
Peripherals.Counter.latched_wallclock_time = 0;
Peripherals.Counter.latched_wallclock_time_split = 0;
Peripherals.Counter.visible_latch_register = 0;
}