sim65: add tracing, and a sim65 control peripheral for sim65 runtime control.

This PR is the first of two PRs that replaces earlier PRs #2589 and #2590.
Due to a git branching mishap it was decided to re-partition the new
functionality in two sequential PRs that offer self-contained, new
functionality to sim65.

The functionality in this first PR extends the sim65 simulator in the following ways:

(1) It provides tracing functionality, i.e., the possibility of printing one line of simulator state information per instruction executed.
(2) It provides a memory mapped "sim65 control" peripheral that allows control of (a) the tracing functionality, and (b) the cpu mode.
(3) It provides command-line options to sim65 to enable the tracing, and to override the CPU mode as specified in the program file header.

More detailed information and some discussion can be found in the discussions with the (now retracted) PRs #2589 and #2590.

This PR provides the technical infrastructure inside the sim65 simulator program itself. Once this PR is accepted, a follow-up PR will be posted that adds C and assembly-language support for the new tracing and peripheral features so they can be easily accessed from the CC65 compiler and the CA65 assembler; some examples; and the documentation for these features. The lack of the latter, in this pull request, will be addressed then.

src/sim65/6502.c

@@ -42,14 +42,16 @@
  * the WAI ($CB) and STP ($DB) instructions are unsupported.
  */
 
-#include <stdbool.h>
 #include <stdint.h>
+#include <stdbool.h>
 
 #include "memory.h"
 #include "peripherals.h"
 #include "error.h"
-#include "6502.h"
 #include "paravirt.h"
+#include "trace.h"
+
+#include "6502.h"
 
 /*
 
@@ -4485,7 +4487,7 @@ static const OPFunc OP65C02Table[256] = {
     OPC_6502_41,
     OPC_65C02_NOP22,    // $42
     OPC_65C02_NOP11,    // $43
-    OPC_6502X_44,        // $44
+    OPC_6502X_44,       // $44
     OPC_6502_45,
     OPC_6502_46,
     OPC_65C02_47,
@@ -4730,6 +4732,10 @@ unsigned ExecuteInsn (void)
     /* If we have an NMI request, handle it */
     if (HaveNMIRequest) {
 
+        if (TraceMode != TRACE_DISABLED) {
+            PrintTraceNMI ();
+        }
+
         HaveNMIRequest = false;
         Peripherals.Counter.NmiEvents += 1;
 
@@ -4746,6 +4752,10 @@ unsigned ExecuteInsn (void)
 
     } else if (HaveIRQRequest && GET_IF () == 0) {
 
+        if (TraceMode != TRACE_DISABLED) {
+            PrintTraceIRQ ();
+        }
+
         HaveIRQRequest = false;
         Peripherals.Counter.IrqEvents += 1;
 
@@ -4765,11 +4775,16 @@ unsigned ExecuteInsn (void)
         /* Normal instruction - read the next opcode */
         uint8_t OPC = MemReadByte (Regs.PC);
 
-        /* Execute it */
-        Handlers[CPU][OPC] ();
+        /* Print a trace line, if trace mode is enabled. */
+        if (TraceMode != TRACE_DISABLED) {
+            PrintTraceInstruction ();
+        }
 
-        /* Increment the instruction counter by one.NMIs and IRQs are counted separately. */
+        /* Increment the instruction counter by one. */
         Peripherals.Counter.CpuInstructions += 1;
+
+        /* Execute the instruction. The handler sets the 'Cycles' variable. */
+        Handlers[CPU][OPC] ();
     }
 
     /* Increment the 64-bit clock cycle counter with the cycle count for the instruction that we just executed. */