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Removed (pretty inconsistently used) tab chars from source code base.

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This commit is contained in:
Oliver Schmidt
2013-05-09 13:56:54 +02:00
parent 44fd1082ae
commit 85885001b1
1773 changed files with 62864 additions and 62868 deletions
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222
libsrc/lynx/eeprom46.s
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@@ -8,7 +8,7 @@
; 16.02.96 leaner (thanks to Harry)
; 12.03.96 test for busy after write and erase (well, Harry ;)) )
; 22.08.97 ported to ra65 for use with cc65
; 02.12.97 added xref for the new ra65
; 02.12.97 added xref for the new ra65
;
;
; (c) 1995..97 Bastian Schick
@@ -25,9 +25,9 @@
; +---| DI |- NC
;(32) AUDIN ----+---| DO |- GND
; ----------
.export _lynx_eeread_93c46
.export _lynx_eeread_93c46
.export _lynx_eewrite_93c46
.import popax
.import popax
.importzp ptr1
.include "lynx.inc"
@@ -45,160 +45,160 @@ EE_C_EWDS = $00
; /* Read a 16 bit word from the given address */
;
_lynx_eeread_93c46:
and #$3f
ora #EE_C_READ
jsr EE_Send9Bit
jsr EE_Read16Bit
lda ptr1
ldx ptr1+1
rts
and #$3f
ora #EE_C_READ
jsr EE_Send9Bit
jsr EE_Read16Bit
lda ptr1
ldx ptr1+1
rts
;***************
; reads EEPROM-word to ptr1
; A,Y destroyed
EE_Read16Bit:
lda #$a
sta IODIR ; set AUDIN to Input
clc
stz ptr1
stz ptr1+1
ldy #15
lda #$a
sta IODIR ; set AUDIN to Input
clc
stz ptr1
stz ptr1+1
ldy #15
EEloop1:
; CLK = 1
stz RCART0
stz RCART0
stz RCART0
stz RCART0
; CLK = 0
stz RCART0
stz RCART0
stz RCART0
stz RCART0
lda IODAT
and #$10 ; mask bit
adc #$f0 ; C=1 if A=$10
rol ptr1
rol ptr1+1 ; shifts 0 to Carry
dey
bpl EEloop1
lda IODAT
and #$10 ; mask bit
adc #$f0 ; C=1 if A=$10
rol ptr1
rol ptr1+1 ; shifts 0 to Carry
dey
bpl EEloop1
ldx #$1a
stx IODIR ; set AUDIN for output
ldx #$1a
stx IODIR ; set AUDIN for output
;EE_SET_CS_LOW
ldx #3
stx SYSCTL1
dex
stx SYSCTL1
ldx #3
stx SYSCTL1
dex
stx SYSCTL1
rts
rts
;***************
; write word to EEPROM
; void __fastcall__ lynx_eewrite_93c46(unsigned int addr, unsigned int val);
_lynx_eewrite_93c46:
sta ptr1
stx ptr1+1
lda #EE_C_EWEN
jsr EE_Send9Bit
jsr popax
and #$3f
ora #EE_C_WRITE
jsr EE_Send9Bit
jsr EE_Send16Bit ; Sends ptr1 that contains val
sta ptr1
stx ptr1+1
lda #EE_C_EWEN
jsr EE_Send9Bit
jsr popax
and #$3f
ora #EE_C_WRITE
jsr EE_Send9Bit
jsr EE_Send16Bit ; Sends ptr1 that contains val
EE_wait:
; EE_SET_CS_HIGH
ldx #63
ldx #63
EEloop:
stz RCART0
stz RCART0
dex
bpl EEloop
stz RCART0
stz RCART0
dex
bpl EEloop
lda #$0A
sta IODIR ; AUDIN to input
lda #$10
lda #$0A
sta IODIR ; AUDIN to input
lda #$10
EE_wait1:
bit IODAT ; 'til ready :D0-read is /D0-written
beq EE_wait1
lda #$1a ; AUDIN to output
sta IODIR
lda #EE_C_EWDS
; bra EE_Send9Bit ; fall into
bit IODAT ; 'til ready :D0-read is /D0-written
beq EE_wait1
lda #$1a ; AUDIN to output
sta IODIR
lda #EE_C_EWDS
; bra EE_Send9Bit ; fall into
;***************
; send A via I2C
; A,Y destroyed
;***************
EE_Send9Bit:
; EE_SET_CS_LOW
ldy #3
sty SYSCTL1
dey
sty SYSCTL1
ldy #3
sty SYSCTL1
dey
sty SYSCTL1
; EE_SET_CS_HIGH
ldy #63
ldy #63
EEloop2:
stz RCART0
stz RCART0
dey
bpl EEloop2
stz RCART0
stz RCART0
dey
bpl EEloop2
ldy #8
sec ; start bit
ror A
ror A
ror A
ror A ; bit 8 at pos. 4
ldy #8
sec ; start bit
ror A
ror A
ror A
ror A ; bit 8 at pos. 4
EEloop3:
tax
and #$10
ora #$b
sta IODAT
tax
and #$10
ora #$b
sta IODAT
; CLK = 1
stz RCART0
stz RCART0
stz RCART0
stz RCART0
; CLK = 0
stz RCART0
stz RCART0
txa
rol A
dey
bpl EEloop3
rts
stz RCART0
stz RCART0
txa
rol A
dey
bpl EEloop3
rts
;***************
; send ptr1 to EEPROM
EE_Send16Bit:
lda ptr1+1
lda ptr1+1
ror A
ror ptr1
ror A
ror ptr1
ror A
ror ptr1
ror A
ror ptr1
ror A
ror ptr1
ror A
ror ptr1
ldy #15
ldy #15
EEloop5:
tax
and #$10
ora #$b
sta IODAT
tax
and #$10
ora #$b
sta IODAT
; CLK = 1
stz RCART0
stz RCART0
stz RCART0
stz RCART0
; CLK = 0
stz RCART0
stz RCART0
txa
rol ptr1
rol A
dey
bpl EEloop5
stz RCART0
stz RCART0
txa
rol ptr1
rol A
dey
bpl EEloop5
; EE_SET_CS_LOW
ldx #3
stx SYSCTL1
dex
stx SYSCTL1
rts
ldx #3
stx SYSCTL1
dex
stx SYSCTL1
rts