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Added decimal mode (untested): http://www.6502.org/tutorials/decimal_mode.html

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git-svn-id: svn://svn.cc65.org/cc65/trunk@4327 b7a2c559-68d2-44c3-8de9-860c34a00d81
This commit is contained in:
uz
2009-10-04 18:52:10 +00:00
parent ca5ada12ba
commit 8b7c9fdc4f
1 changed files with 160 additions and 127 deletions
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287
src/sim65/cpucore.c
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@@ -124,11 +124,11 @@ static char BreakMsg[1024];
#define PAGE_CROSS(addr,offs) ((((addr) & 0xFF) + offs) >= 0x100) #define PAGE_CROSS(addr,offs) ((((addr) & 0xFF) + offs) >= 0x100)
/* #imm */ /* #imm */
#define AC_OP_IMM(op) \ #define AC_OP_IMM(op) \
Cycles = 2; \ Cycles = 2; \
Regs.AC = Regs.AC op MemReadByte (Regs.PC+1); \ Regs.AC = Regs.AC op MemReadByte (Regs.PC+1); \
TEST_ZF (Regs.AC); \ TEST_ZF (Regs.AC); \
TEST_SF (Regs.AC); \ TEST_SF (Regs.AC); \
Regs.PC += 2 Regs.PC += 2
/* zp */ /* zp */
@@ -140,163 +140,196 @@ static char BreakMsg[1024];
Regs.PC += 2 Regs.PC += 2
/* zp,x */ /* zp,x */
#define AC_OP_ZPX(op) \ #define AC_OP_ZPX(op) \
unsigned char ZPAddr; \ unsigned char ZPAddr; \
Cycles = 4; \ Cycles = 4; \
ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; \ ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; \
Regs.AC = Regs.AC op MemReadByte (ZPAddr); \ Regs.AC = Regs.AC op MemReadByte (ZPAddr); \
TEST_ZF (Regs.AC); \ TEST_ZF (Regs.AC); \
TEST_SF (Regs.AC); \ TEST_SF (Regs.AC); \
Regs.PC += 2 Regs.PC += 2
/* zp,y */ /* zp,y */
#define AC_OP_ZPY(op) \ #define AC_OP_ZPY(op) \
unsigned char ZPAddr; \ unsigned char ZPAddr; \
Cycles = 4; \ Cycles = 4; \
ZPAddr = MemReadByte (Regs.PC+1) + Regs.YR; \ ZPAddr = MemReadByte (Regs.PC+1) + Regs.YR; \
Regs.AC = Regs.AC op MemReadByte (ZPAddr); \ Regs.AC = Regs.AC op MemReadByte (ZPAddr); \
TEST_ZF (Regs.AC); \ TEST_ZF (Regs.AC); \
TEST_SF (Regs.AC); \ TEST_SF (Regs.AC); \
Regs.PC += 2 Regs.PC += 2
/* abs */ /* abs */
#define AC_OP_ABS(op) \ #define AC_OP_ABS(op) \
unsigned Addr; \ unsigned Addr; \
Cycles = 4; \ Cycles = 4; \
Addr = MemReadWord (Regs.PC+1); \ Addr = MemReadWord (Regs.PC+1); \
Regs.AC = Regs.AC op MemReadByte (Addr); \ Regs.AC = Regs.AC op MemReadByte (Addr); \
TEST_ZF (Regs.AC); \ TEST_ZF (Regs.AC); \
TEST_SF (Regs.AC); \ TEST_SF (Regs.AC); \
Regs.PC += 3 Regs.PC += 3
/* abs,x */ /* abs,x */
#define AC_OP_ABSX(op) \ #define AC_OP_ABSX(op) \
unsigned Addr; \ unsigned Addr; \
Cycles = 4; \ Cycles = 4; \
Addr = MemReadWord (Regs.PC+1); \ Addr = MemReadWord (Regs.PC+1); \
if (PAGE_CROSS (Addr, Regs.XR)) { \ if (PAGE_CROSS (Addr, Regs.XR)) { \
++Cycles; \ ++Cycles; \
} \ } \
Regs.AC = Regs.AC op MemReadByte (Addr + Regs.XR); \ Regs.AC = Regs.AC op MemReadByte (Addr + Regs.XR); \
TEST_ZF (Regs.AC); \ TEST_ZF (Regs.AC); \
TEST_SF (Regs.AC); \ TEST_SF (Regs.AC); \
Regs.PC += 3 Regs.PC += 3
/* abs,y */ /* abs,y */
#define AC_OP_ABSY(op) \ #define AC_OP_ABSY(op) \
unsigned Addr; \ unsigned Addr; \
Cycles = 4; \ Cycles = 4; \
Addr = MemReadWord (Regs.PC+1); \ Addr = MemReadWord (Regs.PC+1); \
if (PAGE_CROSS (Addr, Regs.YR)) { \ if (PAGE_CROSS (Addr, Regs.YR)) { \
++Cycles; \ ++Cycles; \
} \ } \
Regs.AC = Regs.AC op MemReadByte (Addr + Regs.YR); \ Regs.AC = Regs.AC op MemReadByte (Addr + Regs.YR); \
TEST_ZF (Regs.AC); \ TEST_ZF (Regs.AC); \
TEST_SF (Regs.AC); \ TEST_SF (Regs.AC); \
Regs.PC += 3 Regs.PC += 3
/* (zp,x) */ /* (zp,x) */
#define AC_OP_ZPXIND(op) \ #define AC_OP_ZPXIND(op) \
unsigned char ZPAddr; \ unsigned char ZPAddr; \
unsigned Addr; \ unsigned Addr; \
Cycles = 6; \ Cycles = 6; \
ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; \ ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; \
Addr = MemReadZPWord (ZPAddr); \ Addr = MemReadZPWord (ZPAddr); \
Regs.AC = Regs.AC op MemReadByte (Addr); \ Regs.AC = Regs.AC op MemReadByte (Addr); \
TEST_ZF (Regs.AC); \ TEST_ZF (Regs.AC); \
TEST_SF (Regs.AC); \ TEST_SF (Regs.AC); \
Regs.PC += 2 Regs.PC += 2
/* (zp),y */ /* (zp),y */
#define AC_OP_ZPINDY(op) \ #define AC_OP_ZPINDY(op) \
unsigned char ZPAddr; \ unsigned char ZPAddr; \
unsigned Addr; \ unsigned Addr; \
Cycles = 5; \ Cycles = 5; \
ZPAddr = MemReadByte (Regs.PC+1); \ ZPAddr = MemReadByte (Regs.PC+1); \
Addr = MemReadZPWord (ZPAddr) + Regs.YR; \ Addr = MemReadZPWord (ZPAddr) + Regs.YR; \
Regs.AC = Regs.AC op MemReadByte (Addr); \ Regs.AC = Regs.AC op MemReadByte (Addr); \
TEST_ZF (Regs.AC); \ TEST_ZF (Regs.AC); \
TEST_SF (Regs.AC); \ TEST_SF (Regs.AC); \
Regs.PC += 2 Regs.PC += 2
/* ADC */ /* ADC */
#define ADC(v) \ #define ADC(v) \
if (GET_DF ()) { \ do { \
Warning ("Decimal mode not available"); \ unsigned old = Regs.AC; \
} else { \ unsigned rhs = (v & 0xFF); \
unsigned old = Regs.AC; \ if (GET_DF ()) { \
unsigned rhs = (v & 0xFF); \ unsigned lo; \
Regs.AC += rhs + GET_CF (); \ int res; \
TEST_ZF (Regs.AC); \ lo = (old & 0x0F) + (rhs & 0x0F) + GET_CF (); \
TEST_SF (Regs.AC); \ if (lo >= 0x0A) { \
TEST_CF (Regs.AC); \ lo = ((lo + 0x06) & 0x0F) + 0x10; \
SET_OF (!((old ^ rhs) & 0x80) && \ } \
((old ^ Regs.AC) & 0x80)); \ Regs.AC = (old & 0xF0) + (rhs & 0xF0) + lo; \
Regs.AC &= 0xFF; \ res = (signed char)(old & 0xF0) + \
} (signed char)(rhs & 0xF0) + \
(signed char)lo; \
TEST_ZF (old + rhs + GET_CF ()); \
TEST_SF (Regs.AC); \
if (Regs.AC >= 0xA0) { \
Regs.AC += 0x60; \
} \
TEST_CF (Regs.AC); \
SET_OF ((res < -128) || (res > 127)); \
} else { \
Regs.AC += rhs + GET_CF (); \
TEST_ZF (Regs.AC); \
TEST_SF (Regs.AC); \
TEST_CF (Regs.AC); \
SET_OF (!((old ^ rhs) & 0x80) && \
((old ^ Regs.AC) & 0x80)); \
Regs.AC &= 0xFF; \
} \
} while (0)
/* branches */ /* branches */
#define BRANCH(cond) \ #define BRANCH(cond) \
Cycles = 2; \ Cycles = 2; \
if (cond) { \ if (cond) { \
signed char Offs; \ signed char Offs; \
unsigned char OldPCH; \ unsigned char OldPCH; \
++Cycles; \ ++Cycles; \
Offs = (signed char) MemReadByte (Regs.PC+1); \ Offs = (signed char) MemReadByte (Regs.PC+1); \
OldPCH = PCH; \ OldPCH = PCH; \
Regs.PC += 2 + (int) Offs; \ Regs.PC += 2 + (int) Offs; \
if (PCH != OldPCH) { \ if (PCH != OldPCH) { \
++Cycles; \ ++Cycles; \
} \ } \
} else { \ } else { \
Regs.PC += 2; \ Regs.PC += 2; \
} }
/* compares */ /* compares */
#define CMP(v1,v2) \ #define CMP(v1,v2) \
{ \ do { \
unsigned Result = v1 - v2; \ unsigned Result = v1 - v2; \
TEST_ZF (Result & 0xFF); \ TEST_ZF (Result & 0xFF); \
TEST_SF (Result); \ TEST_SF (Result); \
SET_CF (Result <= 0xFF); \ SET_CF (Result <= 0xFF); \
} } while (0)
/* ROL */ /* ROL */
#define ROL(Val) \ #define ROL(Val) \
Val <<= 1; \ Val <<= 1; \
if (GET_CF ()) { \ if (GET_CF ()) { \
Val |= 0x01; \ Val |= 0x01; \
} \ } \
TEST_ZF (Val); \ TEST_ZF (Val); \
TEST_SF (Val); \ TEST_SF (Val); \
TEST_CF (Val) TEST_CF (Val)
/* ROR */ /* ROR */
#define ROR(Val) \ #define ROR(Val) \
if (GET_CF ()) { \ if (GET_CF ()) { \
Val |= 0x100; \ Val |= 0x100; \
} \ } \
SET_CF (Val & 0x01); \ SET_CF (Val & 0x01); \
Val >>= 1; \ Val >>= 1; \
TEST_ZF (Val); \ TEST_ZF (Val); \
TEST_SF (Val) TEST_SF (Val)
/* SBC */ /* SBC */
#define SBC(v) \ #define SBC(v) \
if (GET_DF ()) { \ do { \
Warning ("Decimal mode not available"); \ unsigned old = Regs.AC; \
} else { \ unsigned rhs = (v & 0xFF); \
unsigned old = Regs.AC; \ if (GET_DF ()) { \
unsigned rhs = (v & 0xFF); \ unsigned lo; \
Regs.AC -= rhs - (!GET_CF ()); \ int res; \
TEST_ZF (Regs.AC); \ lo = (old & 0x0F) - (rhs & 0x0F) + GET_CF () - 1; \
TEST_SF (Regs.AC); \ if (lo & 0x80) { \
SET_CF (Regs.AC <= 0xFF); \ lo = ((lo - 0x06) & 0x0F) - 0x10; \
SET_OF (((old^rhs) & (old^Regs.AC) & 0x80)); \ } \
Regs.AC &= 0xFF; \ Regs.AC = (old & 0xF0) - (rhs & 0xF0) + lo; \
} if (Regs.AC & 0x80) { \
Regs.AC -= 0x60; \
} \
res = Regs.AC - rhs + (!GET_CF ()); \
TEST_ZF (res); \
TEST_SF (res); \
SET_CF (res <= 0xFF); \
SET_OF (((old^rhs) & (old^res) & 0x80)); \
} else { \
Regs.AC -= rhs - (!GET_CF ()); \
TEST_ZF (Regs.AC); \
TEST_SF (Regs.AC); \
SET_CF (Regs.AC <= 0xFF); \
SET_OF (((old^rhs) & (old^Regs.AC) & 0x80)); \
Regs.AC &= 0xFF; \
} \
} while (0)
/*****************************************************************************/ /*****************************************************************************/