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part of #1792 - 48GS02 assembler support

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This commit is contained in:
mrdudz
2025-06-21 00:56:34 +02:00
parent d333627081
commit 9344d87b05
14 changed files with 803 additions and 74 deletions
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11
src/ca65/condasm.c
View File

@@ -414,6 +414,16 @@ void DoConditionals (void)
CalcOverallIfCond ();
break;
case TOK_IFP45GS02:
D = AllocIf (".IFP45GS02", 1);
NextTok ();
if (IfCond) {
SetIfCond (D, GetCPU() == CPU_45GS02);
}
ExpectSep ();
CalcOverallIfCond ();
break;
case TOK_IFP816:
D = AllocIf (".IFP816", 1);
NextTok ();
@@ -507,6 +517,7 @@ int CheckConditionals (void)
case TOK_IFP02:
case TOK_IFP02X:
case TOK_IFP4510:
case TOK_IFP45GS02:
case TOK_IFP816:
case TOK_IFPC02:
case TOK_IFPDTV:

33
src/ca65/ea65.c
View File

@@ -101,6 +101,9 @@ void GetEA (EffAddr* A)
if (TokIsSep (CurTok.Tok)) {
A->AddrModeSet = AM65_IMPLICIT;
if (GetCPU() == CPU_45GS02) {
A->AddrModeSet |= AM65_Q;
}
} else if (CurTok.Tok == TOK_HASH) {
@@ -114,6 +117,11 @@ void GetEA (EffAddr* A)
NextTok ();
A->AddrModeSet = AM65_ACCU;
} else if (CurTok.Tok == TOK_Q) {
NextTok ();
A->AddrModeSet = AM65_Q;
} else if (CurTok.Tok == IndirectEnter) {
/* One of the indirect modes */
@@ -160,8 +168,19 @@ void GetEA (EffAddr* A)
}
} else {
/* (adr) */
A->AddrModeSet = (CPU == CPU_4510) ? AM65_ABS_IND
: AM65_ABS_IND | AM65_ABS_IND_LONG | AM65_DIR_IND;
switch (CPU) {
case CPU_4510:
A->AddrModeSet = AM65_ABS_IND;
break;
case CPU_45GS02:
A->AddrModeSet = AM65_ABS_IND | AM65_DIR_IND;
break;
default:
A->AddrModeSet = AM65_ABS_IND | AM65_ABS_IND_LONG | AM65_DIR_IND;
break;
}
}
}
@@ -175,8 +194,14 @@ void GetEA (EffAddr* A)
if (CurTok.Tok == TOK_COMMA) {
/* [dir],y */
NextTok ();
Consume (TOK_Y, "'Y' expected");
A->AddrModeSet = AM65_DIR_IND_LONG_Y;
if (GetCPU() == CPU_45GS02) {
Consume(TOK_Z, "'Z' expected");
A->AddrModeSet = AM65_32BIT_BASE_IND_Z;
}
else {
Consume(TOK_Y, "'Y' expected");
A->AddrModeSet = AM65_DIR_IND_LONG_Y;
}
} else {
/* [dir] */
A->AddrModeSet = AM65_DIR_IND_LONG | AM65_ABS_IND_LONG;

317
src/ca65/instr.c
View File

@@ -154,6 +154,12 @@ static void PutAll (const InsDesc* Ins);
static void Put4510 (const InsDesc* Ins);
/* Handle instructions of 4510 not matching any EATab */
static void Put45GS02 (const InsDesc* Ins);
/* Handle [adr],z instructions of 45GS02 */
static void Put45GS02_Q (const InsDesc* Ins);
/* Handle Q instructions of 45GS02 */
static void PutSweet16 (const InsDesc* Ins);
/* Handle a generic sweet16 instruction */
@@ -758,6 +764,170 @@ static const struct {
}
};
/* Instruction table for the 45GS02 */
static const struct {
unsigned Count;
InsDesc Ins[149];
} InsTab45GS02 = {
/* CAUTION: table must be sorted for bsearch */
sizeof (InsTab45GS02.Ins) / sizeof (InsTab45GS02.Ins[0]),
{
/* BEGIN SORTED.SH */
{ "ADC", 0x4080A66C, 0x60, 0, Put45GS02 },
{ "ADCQ", 0x0000140C, 0x60, 13, Put45GS02_Q },
{ "AND", 0x4080A66C, 0x20, 0, Put45GS02 },
{ "ANDQ", 0x0000140C, 0x20, 13, Put45GS02_Q },
{ "ASL", 0x0000006e, 0x02, 1, PutAll },
{ "ASLQ", 0x800000ec, 0x00, 14, Put45GS02_Q },
{ "ASR", 0x00000026, 0x43, 0, Put4510 },
{ "ASRQ", 0x80000024, 0x40, 15, Put45GS02_Q },
{ "ASW", 0x00000008, 0xcb, 6, PutAll },
{ "BBR0", 0x00000000, 0x0F, 0, PutBitBranch },
{ "BBR1", 0x00000000, 0x1F, 0, PutBitBranch },
{ "BBR2", 0x00000000, 0x2F, 0, PutBitBranch },
{ "BBR3", 0x00000000, 0x3F, 0, PutBitBranch },
{ "BBR4", 0x00000000, 0x4F, 0, PutBitBranch },
{ "BBR5", 0x00000000, 0x5F, 0, PutBitBranch },
{ "BBR6", 0x00000000, 0x6F, 0, PutBitBranch },
{ "BBR7", 0x00000000, 0x7F, 0, PutBitBranch },
{ "BBS0", 0x00000000, 0x8F, 0, PutBitBranch },
{ "BBS1", 0x00000000, 0x9F, 0, PutBitBranch },
{ "BBS2", 0x00000000, 0xAF, 0, PutBitBranch },
{ "BBS3", 0x00000000, 0xBF, 0, PutBitBranch },
{ "BBS4", 0x00000000, 0xCF, 0, PutBitBranch },
{ "BBS5", 0x00000000, 0xDF, 0, PutBitBranch },
{ "BBS6", 0x00000000, 0xEF, 0, PutBitBranch },
{ "BBS7", 0x00000000, 0xFF, 0, PutBitBranch },
{ "BCC", 0x00020000, 0x90, 0, PutPCRel8 },
{ "BCS", 0x00020000, 0xb0, 0, PutPCRel8 },
{ "BEQ", 0x00020000, 0xf0, 0, PutPCRel8 },
{ "BIT", 0x00A0006C, 0x00, 2, PutAll },
{ "BITQ", 0x0000000c, 0x20, 15, Put45GS02_Q },
{ "BMI", 0x00020000, 0x30, 0, PutPCRel8 },
{ "BNE", 0x00020000, 0xd0, 0, PutPCRel8 },
{ "BPL", 0x00020000, 0x10, 0, PutPCRel8 },
{ "BRA", 0x00020000, 0x80, 0, PutPCRel8 },
{ "BRK", 0x00000001, 0x00, 0, PutAll },
{ "BSR", 0x00040000, 0x63, 0, PutPCRel4510 },
{ "BVC", 0x00020000, 0x50, 0, PutPCRel8 },
{ "BVS", 0x00020000, 0x70, 0, PutPCRel8 },
{ "CLC", 0x00000001, 0x18, 0, PutAll },
{ "CLD", 0x00000001, 0xd8, 0, PutAll },
{ "CLE", 0x00000001, 0x02, 0, PutAll },
{ "CLI", 0x00000001, 0x58, 0, PutAll },
{ "CLV", 0x00000001, 0xb8, 0, PutAll },
{ "CMP", 0x4080A66C, 0xc0, 0, Put45GS02 },
{ "CMPQ", 0x0000140C, 0xC0, 13, Put45GS02_Q },
{ "CPX", 0x0080000C, 0xe0, 1, PutAll },
{ "CPY", 0x0080000C, 0xc0, 1, PutAll },
{ "CPZ", 0x0080000C, 0xd0, 1, Put4510 },
{ "DEA", 0x00000001, 0x00, 3, PutAll }, /* == DEC */
{ "DEC", 0x0000006F, 0x00, 3, PutAll },
{ "DEQ", 0x800000ec, 0xc0, 14, Put45GS02_Q },
{ "DEW", 0x00000004, 0xc3, 9, PutAll },
{ "DEX", 0x00000001, 0xca, 0, PutAll },
{ "DEY", 0x00000001, 0x88, 0, PutAll },
{ "DEZ", 0x00000001, 0x3B, 0, PutAll },
{ "EOM", 0x00000001, 0xea, 0, PutAll },
{ "EOR", 0x4080A66C, 0x40, 0, Put45GS02 },
{ "EORQ", 0x0000140C, 0x40, 13, Put45GS02_Q },
{ "INA", 0x00000001, 0x00, 4, PutAll }, /* == INC */
{ "INC", 0x0000006f, 0x00, 4, PutAll },
{ "INQ", 0x800000ec, 0xe0, 14, Put45GS02_Q },
{ "INW", 0x00000004, 0xe3, 9, PutAll },
{ "INX", 0x00000001, 0xe8, 0, PutAll },
{ "INY", 0x00000001, 0xc8, 0, PutAll },
{ "INZ", 0x00000001, 0x1B, 0, PutAll },
{ "JMP", 0x00010808, 0x4c, 6, PutAll },
{ "JSR", 0x00010808, 0x20, 7, Put4510 },
{ "LBCC", 0x00040000, 0x93, 0, PutPCRel4510 },
{ "LBCS", 0x00040000, 0xb3, 0, PutPCRel4510 },
{ "LBEQ", 0x00040000, 0xf3, 0, PutPCRel4510 },
{ "LBMI", 0x00040000, 0x33, 0, PutPCRel4510 },
{ "LBNE", 0x00040000, 0xd3, 0, PutPCRel4510 },
{ "LBPL", 0x00040000, 0x13, 0, PutPCRel4510 },
{ "LBRA", 0x00040000, 0x83, 0, PutPCRel4510 },
{ "LBVC", 0x00040000, 0x53, 0, PutPCRel4510 },
{ "LBVS", 0x00040000, 0x73, 0, PutPCRel4510 },
{ "LDA", 0x4090A66C, 0xa0, 0, Put45GS02 },
{ "LDQ", 0x4000140C, 0xa0, 13, Put45GS02_Q },
{ "LDX", 0x0080030C, 0xa2, 1, PutAll },
{ "LDY", 0x0080006C, 0xa0, 1, PutAll },
{ "LDZ", 0x00800048, 0xa3, 1, Put4510 },
{ "LSR", 0x0000006F, 0x42, 1, PutAll },
{ "LSRQ", 0x800000ec, 0x40, 14, Put45GS02_Q },
{ "MAP", 0x00000001, 0x5C, 0, PutAll },
{ "NEG", 0x00000001, 0x42, 0, PutAll },
{ "NOP", 0x00000001, 0xea, 0, PutAll }, /* == EOM */
{ "ORA", 0x4080A66C, 0x00, 0, Put45GS02 },
{ "ORQ", 0x0000140C, 0x00, 13, Put45GS02_Q },
{ "PHA", 0x00000001, 0x48, 0, PutAll },
{ "PHD", 0x08000008, 0xf4, 1, PutAll }, /* == PHW */
{ "PHP", 0x00000001, 0x08, 0, PutAll },
{ "PHW", 0x08000008, 0xf4, 1, PutAll },
{ "PHX", 0x00000001, 0xda, 0, PutAll },
{ "PHY", 0x00000001, 0x5a, 0, PutAll },
{ "PHZ", 0x00000001, 0xdb, 0, PutAll },
{ "PLA", 0x00000001, 0x68, 0, PutAll },
{ "PLP", 0x00000001, 0x28, 0, PutAll },
{ "PLX", 0x00000001, 0xfa, 0, PutAll },
{ "PLY", 0x00000001, 0x7a, 0, PutAll },
{ "PLZ", 0x00000001, 0xfb, 0, PutAll },
{ "RMB0", 0x00000004, 0x07, 1, PutAll },
{ "RMB1", 0x00000004, 0x17, 1, PutAll },
{ "RMB2", 0x00000004, 0x27, 1, PutAll },
{ "RMB3", 0x00000004, 0x37, 1, PutAll },
{ "RMB4", 0x00000004, 0x47, 1, PutAll },
{ "RMB5", 0x00000004, 0x57, 1, PutAll },
{ "RMB6", 0x00000004, 0x67, 1, PutAll },
{ "RMB7", 0x00000004, 0x77, 1, PutAll },
{ "ROL", 0x0000006F, 0x22, 1, PutAll },
{ "ROLQ", 0x800000ec, 0x20, 14, Put45GS02_Q },
{ "ROR", 0x0000006F, 0x62, 1, PutAll },
{ "RORQ", 0x800000ec, 0x60, 14, Put45GS02_Q },
{ "ROW", 0x00000008, 0xeb, 6, PutAll },
{ "RTI", 0x00000001, 0x40, 0, PutAll },
{ "RTN", 0x00800000, 0x62, 1, PutAll },
{ "RTS", 0x00000001, 0x60, 0, PutAll },
{ "SBC", 0x4080A66C, 0xe0, 0, Put45GS02 },
{ "SBCQ", 0x0000140C, 0xe0, 13, Put45GS02_Q },
{ "SEC", 0x00000001, 0x38, 0, PutAll },
{ "SED", 0x00000001, 0xf8, 0, PutAll },
{ "SEE", 0x00000001, 0x03, 0, PutAll },
{ "SEI", 0x00000001, 0x78, 0, PutAll },
{ "SMB0", 0x00000004, 0x87, 1, PutAll },
{ "SMB1", 0x00000004, 0x97, 1, PutAll },
{ "SMB2", 0x00000004, 0xA7, 1, PutAll },
{ "SMB3", 0x00000004, 0xB7, 1, PutAll },
{ "SMB4", 0x00000004, 0xC7, 1, PutAll },
{ "SMB5", 0x00000004, 0xD7, 1, PutAll },
{ "SMB6", 0x00000004, 0xE7, 1, PutAll },
{ "SMB7", 0x00000004, 0xF7, 1, PutAll },
{ "STA", 0x4010A66C, 0x80, 0, Put45GS02 },
{ "STQ", 0x0000140C, 0x80, 13, Put45GS02_Q },
{ "STX", 0x0000030c, 0x82, 1, Put4510 },
{ "STY", 0x0000006c, 0x80, 1, Put4510 },
{ "STZ", 0x0000006c, 0x04, 5, PutAll },
{ "TAB", 0x00000001, 0x5b, 0, PutAll },
{ "TAX", 0x00000001, 0xaa, 0, PutAll },
{ "TAY", 0x00000001, 0xa8, 0, PutAll },
{ "TAZ", 0x00000001, 0x4b, 0, PutAll },
{ "TBA", 0x00000001, 0x7b, 0, PutAll },
{ "TRB", 0x0000000c, 0x10, 1, PutAll },
{ "TSB", 0x0000000c, 0x00, 1, PutAll },
{ "TSX", 0x00000001, 0xba, 0, PutAll },
{ "TSY", 0x00000001, 0x0b, 0, PutAll },
{ "TXA", 0x00000001, 0x8a, 0, PutAll },
{ "TXS", 0x00000001, 0x9a, 0, PutAll },
{ "TYA", 0x00000001, 0x98, 0, PutAll },
{ "TYS", 0x00000001, 0x2b, 0, PutAll },
{ "TZA", 0x00000001, 0x6b, 0, PutAll },
/* END SORTED.SH */
}
};
/* Instruction table for the 65816 */
static const struct {
unsigned Count;
@@ -1192,6 +1362,7 @@ static const InsTable* InsTabs[CPU_COUNT] = {
(const InsTable*) &InsTabHuC6280,
(const InsTable*) &InsTabm740, /* Mitsubishi 740 */
(const InsTable*) &InsTab4510,
(const InsTable*) &InsTab45GS02,
};
const InsTable* InsTab = (const InsTable*) &InsTab6502;
@@ -1199,85 +1370,103 @@ const InsTable* InsTab = (const InsTable*) &InsTab6502;
** addressing mode. (The value in the table is ORed with the base opcode)
** NOTE: each table has one entry per addressing mode!
*/
static unsigned char EATab[14][AM65I_COUNT] = {
static unsigned char EATab[16][AM65I_COUNT] = {
{ /* Table 0 (sec, sed, seo, set, slw, sta, stp, tax, tay, tsx, txa, txs, tya) */
0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F,
0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01,
0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00
},
{ /* Table 1 (rol, ror, stx, sty, tst) */
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x80, 0x00, 0x00, 0x00
0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 2 (bit) */
0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 3 (dec, dea) */
0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 4 (inc) */
0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 5 (stz) */
0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 6 (jmp, rrf) */
0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x90, 0x00, 0x00, 0x00
0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 7 (jsr) */
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 8 */
0x00, 0x40, 0x01, 0x41, 0x00, 0x09, 0x49, 0x00,
0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 9 (dew, inw) */
0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 10 (NOPs, clbX, sebX) */
0xea, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x1c, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 11 (LAX) */
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
0x00, 0x00, 0x80, 0x00, 0x00, 0x00
0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 12 (m740: JMP) */
0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0xb2, 0x6c, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 13 (Q) */
0x00, 0x00, 0x05, 0x0D, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00
},
{ /* Table 14 (Q) */
0x00, 0x00, 0x06, 0x0e, 0x00, 0x16, 0x1e, 0x00,
0x00, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a
},
{ /* Table 15 */
0x00, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03
}
};
/* Table to build the effective SWEET16 opcode from a base opcode and an
@@ -1325,6 +1514,8 @@ unsigned char ExtBytes[AM65I_COUNT] = {
2, /* Immidiate word */
2, /* Direct, Relative short */
1, /* Special Page */
1, /* [Direct],z */
0, /* Q */
};
/* Table that encodes the additional bytes for each SWEET16 instruction */
@@ -1968,9 +2159,7 @@ static void PutAll (const InsDesc* Ins)
static void Put4510 (const InsDesc* Ins)
/* Handle all other instructions, with modifications for 4510 */
{
static void Emit4510 (EffAddr* A) {
/* The 4510 uses all 256 possible opcodes, so the last ones were crammed
** in where an opcode was still undefined. As a result, some of those
** don't follow any rules for encoding the addressmodes. So the EATab
@@ -1990,26 +2179,90 @@ static void Put4510 (const InsDesc* Ins)
** $d0 -> $c2 : CPZ #$00
** $fc -> $23 : JSR ($1234,X)
*/
switch (A->Opcode) {
case 0x47:
A->Opcode = 0x44;
break;
case 0x57:
A->Opcode = 0x54;
break;
case 0x93:
A->Opcode = 0x82;
break;
case 0x9C:
A->Opcode = 0x8B;
break;
case 0x9E:
A->Opcode = 0x9B;
break;
case 0xAF:
A->Opcode = 0xAB;
break;
case 0xBF:
A->Opcode = 0xBB;
break;
case 0xB3:
A->Opcode = 0xE2;
break;
case 0xD0:
A->Opcode = 0xC2;
break;
case 0xFC:
A->Opcode = 0x23;
break;
default: /* Keep opcode as it is */ break;
}
/* No error, output code */
EmitCode(A);
}
static void Put4510 (const InsDesc* Ins)
/* Handle all other instructions, with modifications for 4510 */
{
EffAddr A;
/* Evaluate the addressing mode used */
if (EvalEA (Ins, &A)) {
switch (A.Opcode) {
case 0x47: A.Opcode = 0x44; break;
case 0x57: A.Opcode = 0x54; break;
case 0x93: A.Opcode = 0x82; break;
case 0x9C: A.Opcode = 0x8B; break;
case 0x9E: A.Opcode = 0x9B; break;
case 0xAF: A.Opcode = 0xAB; break;
case 0xBF: A.Opcode = 0xBB; break;
case 0xB3: A.Opcode = 0xE2; break;
case 0xD0: A.Opcode = 0xC2; break;
case 0xFC: A.Opcode = 0x23; break;
default: /* Keep opcode as it is */ break;
}
Emit4510(&A);
}
}
/* No error, output code */
EmitCode (&A);
static void Put45GS02 (const InsDesc* Ins)
/* Handle all other instructions, with modifications for 45GS02 */
{
EffAddr A;
if (EvalEA(Ins, &A)) {
if (A.AddrModeSet == AM65_32BIT_BASE_IND_Z) {
Emit0(0xEA); /* NOP prefix */
}
Emit4510(&A);
}
}
static void Put45GS02_Q (const InsDesc* Ins) {
EffAddr A;
if (EvalEA(Ins, &A)) {
Emit0(0x42);
Emit0(0x42);
if ((A.AddrModeBit == AM65_DIR_IND_LONG) || (A.AddrModeBit == AM65_32BIT_BASE_IND_Z)) {
Emit0(0xEA); /* NOP prefix */
}
if (A.Opcode == 0xea) {
A.Opcode = 0x1a;
}
else if (A.Opcode == 0xca) {
A.Opcode = 0x3a;
}
EmitCode(&A);
}
}

40
src/ca65/instr.h
View File

@@ -59,35 +59,37 @@
** available on these CPUs are removed before doing any checks.
*/
#define AM65_IMPLICIT 0x00000003UL /* IMP */
#define AM65_ACCU 0x00000002UL /* A, BIT, A */
#define AM65_DIR 0x00000004UL /* ZP, BIT, ZP */
#define AM65_ACCU 0x00000002UL /* A */
#define AM65_DIR 0x00000004UL /* ZP */
#define AM65_ABS 0x00000008UL /* ABS */
#define AM65_ABS_LONG 0x00000010UL /* -- */
#define AM65_ABS_LONG 0x00000010UL /* adr */
#define AM65_DIR_X 0x00000020UL /* ZP,X */
#define AM65_ABS_X 0x00000040UL /* ABS, X */
#define AM65_ABS_LONG_X 0x00000080UL /* -- */
#define AM65_ABS_LONG_X 0x00000080UL /* adr,x */
#define AM65_DIR_Y 0x00000100UL /* ZP, Y */
#define AM65_ABS_Y 0x00000200UL /* ABS, Y */
#define AM65_DIR_IND 0x00000400UL /* (ZP IND) */
#define AM65_ABS_IND 0x00000800UL /* (IND) */
#define AM65_DIR_IND_LONG 0x00001000UL /* -- */
#define AM65_DIR_IND_Y 0x00002000UL /* IND, Y */
#define AM65_DIR_IND_LONG_Y 0x00004000UL /* -- */
#define AM65_DIR_X_IND 0x00008000UL /* IND, X */
#define AM65_ABS_X_IND 0x00010000UL /* -- */
#define AM65_DIR_IND 0x00000400UL /* (ZP) or (ZP),z (4510 / 45GS02) */
#define AM65_ABS_IND 0x00000800UL /* (ABS) */
#define AM65_DIR_IND_LONG 0x00001000UL /* [ABS] (65816) */
#define AM65_DIR_IND_Y 0x00002000UL /* (ZP),y */
#define AM65_DIR_IND_LONG_Y 0x00004000UL /* [adr],y (not 45GS02) */
#define AM65_DIR_X_IND 0x00008000UL /* (ZP,x) */
#define AM65_ABS_X_IND 0x00010000UL /* (ABS,x) */
#define AM65_REL 0x00020000UL /* REL */
#define AM65_REL_LONG 0x00040000UL /* -- */
#define AM65_STACK_REL 0x00080000UL /* SP ? */
#define AM65_STACK_REL_IND_Y 0x00100000UL /* ? */
#define AM65_REL_LONG 0x00040000UL /* LONGREL */
#define AM65_STACK_REL 0x00080000UL /* adr,s */
#define AM65_STACK_REL_IND_Y 0x00100000UL /* (rel,s),y */
#define AM65_IMM_ACCU 0x00200000UL
#define AM65_IMM_INDEX 0x00400000UL
#define AM65_IMM_IMPLICIT 0x00800000UL /* IMM */
#define AM65_BLOCKMOVE 0x01000000UL /* -- */
#define AM65_BLOCKXFER 0x02000000UL /* -- */
#define AM65_ABS_IND_LONG 0x04000000UL /* -- */
#define AM65_BLOCKMOVE 0x01000000UL
#define AM65_BLOCKXFER 0x02000000UL
#define AM65_ABS_IND_LONG 0x04000000UL /* (adr) [dir] */
#define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */
#define AM65_ZP_REL 0x10000000UL /* ZP, REL (m740) */
#define AM65_SPECIAL_PAGE 0x20000000UL /* $FFxx (m740) */
#define AM65_32BIT_BASE_IND_Z 0x40000000UL /* LDA [$nn],Z (45GS02 only) */
#define AM65_Q 0x80000000UL /* Q (45GS02 only) */
/* Bitmask for all ZP operations that have correspondent ABS ops */
#define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
@@ -138,7 +140,9 @@
#define AM65I_IMM_IMPLICIT_WORD 27
#define AM65I_ZP_REL 28
#define AM65I_SPECIAL_PAGE 29
#define AM65I_COUNT 30
#define AM65I_32BIT_BASE_IND_Z 30
#define AM65I_Q 31
#define AM65I_COUNT 32

10
src/ca65/pseudo.c
View File

@@ -1594,6 +1594,14 @@ static void DoP4510 (void)
static void DoP45GS02 (void)
/* Switch to 45GS02 CPU */
{
SetCPU (CPU_45GS02);
}
static void DoPDTV (void)
/* Switch to C64DTV CPU */
{
@@ -2151,6 +2159,7 @@ static CtrlDesc CtrlCmdTab [] = {
{ ccKeepToken, DoConditionals }, /* .IFP02 */
{ ccKeepToken, DoConditionals }, /* .IFP02X */
{ ccKeepToken, DoConditionals }, /* .IFP4510 */
{ ccKeepToken, DoConditionals }, /* .IFP45GS02 */
{ ccKeepToken, DoConditionals }, /* .IFP816 */
{ ccKeepToken, DoConditionals }, /* .IFPC02 */
{ ccKeepToken, DoConditionals }, /* .IFPDTV */
@@ -2186,6 +2195,7 @@ static CtrlDesc CtrlCmdTab [] = {
{ ccNone, DoP02 }, /* .P02 */
{ ccNone, DoP02X }, /* .P02X */
{ ccNone, DoP4510 }, /* .P4510 */
{ ccNone, DoP45GS02 }, /* .P45GS02 */
{ ccNone, DoP816 }, /* .P816 */
{ ccNone, DoPageLength }, /* .PAGELEN, .PAGELENGTH */
{ ccNone, DoUnexpected }, /* .PARAMCOUNT */

15
src/ca65/scanner.c
View File

@@ -223,6 +223,7 @@ struct DotKeyword {
{ ".IFP02", TOK_IFP02 },
{ ".IFP02X", TOK_IFP02X },
{ ".IFP4510", TOK_IFP4510 },
{ ".IFP45GS02", TOK_IFP45GS02 },
{ ".IFP816", TOK_IFP816 },
{ ".IFPC02", TOK_IFPC02 },
{ ".IFPDTV", TOK_IFPDTV },
@@ -263,6 +264,7 @@ struct DotKeyword {
{ ".P02", TOK_P02 },
{ ".P02X", TOK_P02X },
{ ".P4510", TOK_P4510 },
{ ".P45GS02", TOK_P45GS02 },
{ ".P816", TOK_P816 },
{ ".PAGELEN", TOK_PAGELENGTH },
{ ".PAGELENGTH", TOK_PAGELENGTH },
@@ -1279,12 +1281,19 @@ Again:
break;
case 'S':
if ((CPU == CPU_4510) || (CPU == CPU_65816)) {
if ((CPU == CPU_4510) || (CPU == CPU_45GS02) || (CPU == CPU_65816)) {
CurTok.Tok = TOK_S;
return;
}
break;
case 'Q':
if (CPU == CPU_45GS02) {
CurTok.Tok = TOK_Q;
return;
}
break;
case 'X':
CurTok.Tok = TOK_X;
return;
@@ -1299,7 +1308,7 @@ Again:
CurTok.Tok = TOK_OVERRIDE_ZP;
return;
} else {
if (CPU == CPU_4510) {
if ((CPU == CPU_4510) || (CPU == CPU_45GS02)) {
CurTok.Tok = TOK_Z;
return;
}
@@ -1311,7 +1320,7 @@ Again:
}
break;
case 2:
if ((CPU == CPU_4510) &&
if ((CPU == CPU_4510 || CPU == CPU_45GS02) &&
(toupper (SB_AtUnchecked (&CurTok.SVal, 0)) == 'S') &&
(toupper (SB_AtUnchecked (&CurTok.SVal, 1)) == 'P')) {

3
src/ca65/token.h
View File

@@ -68,6 +68,7 @@ typedef enum token_t {
TOK_Y, /* Y register */
TOK_Z, /* Z register */
TOK_S, /* S register */
TOK_Q, /* Q pseudo register */
TOK_REG, /* Sweet16 R.. register (in sweet16 mode) */
TOK_ASSIGN, /* := */
@@ -195,6 +196,7 @@ typedef enum token_t {
TOK_IFP02,
TOK_IFP02X,
TOK_IFP4510,
TOK_IFP45GS02,
TOK_IFP816,
TOK_IFPC02,
TOK_IFPDTV,
@@ -230,6 +232,7 @@ typedef enum token_t {
TOK_P02,
TOK_P02X,
TOK_P4510,
TOK_P45GS02,
TOK_P816,
TOK_PAGELENGTH,
TOK_PARAMCOUNT,

2
src/common/cpu.c
View File

@@ -63,6 +63,7 @@ const char* CPUNames[CPU_COUNT] = {
"huc6280",
"m740",
"4510",
"45GS02"
};
/* Tables with CPU instruction sets */
@@ -78,6 +79,7 @@ const unsigned CPUIsets[CPU_COUNT] = {
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_HUC6280,
CPU_ISET_6502 | CPU_ISET_M740,
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_4510,
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_4510 | CPU_ISET_45GS02,
};

2
src/common/cpu.h
View File

@@ -58,6 +58,7 @@ typedef enum {
CPU_HUC6280, /* Used in PC engine */
CPU_M740, /* Mitsubishi 740 series MCUs */
CPU_4510, /* CPU of C65 */
CPU_45GS02, /* CPU of MEGA65 */
CPU_COUNT /* Number of different CPUs */
} cpu_t;
@@ -74,6 +75,7 @@ enum {
CPU_ISET_HUC6280 = 1 << CPU_HUC6280,
CPU_ISET_M740 = 1 << CPU_M740,
CPU_ISET_4510 = 1 << CPU_4510,
CPU_ISET_45GS02 = 1 << CPU_45GS02
};
/* CPU used */