part of #1792 - 48GS02 assembler support
This commit is contained in:
mrdudz
317
src/ca65/instr.c
317
src/ca65/instr.c
@@ -154,6 +154,12 @@ static void PutAll (const InsDesc* Ins);
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static void Put4510 (const InsDesc* Ins);
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/* Handle instructions of 4510 not matching any EATab */
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static void Put45GS02 (const InsDesc* Ins);
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/* Handle [adr],z instructions of 45GS02 */
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static void Put45GS02_Q (const InsDesc* Ins);
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/* Handle Q instructions of 45GS02 */
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static void PutSweet16 (const InsDesc* Ins);
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/* Handle a generic sweet16 instruction */
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@@ -758,6 +764,170 @@ static const struct {
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}
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};
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/* Instruction table for the 45GS02 */
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static const struct {
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unsigned Count;
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InsDesc Ins[149];
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} InsTab45GS02 = {
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/* CAUTION: table must be sorted for bsearch */
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sizeof (InsTab45GS02.Ins) / sizeof (InsTab45GS02.Ins[0]),
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{
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/* BEGIN SORTED.SH */
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{ "ADC", 0x4080A66C, 0x60, 0, Put45GS02 },
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{ "ADCQ", 0x0000140C, 0x60, 13, Put45GS02_Q },
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{ "AND", 0x4080A66C, 0x20, 0, Put45GS02 },
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{ "ANDQ", 0x0000140C, 0x20, 13, Put45GS02_Q },
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{ "ASL", 0x0000006e, 0x02, 1, PutAll },
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{ "ASLQ", 0x800000ec, 0x00, 14, Put45GS02_Q },
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{ "ASR", 0x00000026, 0x43, 0, Put4510 },
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{ "ASRQ", 0x80000024, 0x40, 15, Put45GS02_Q },
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{ "ASW", 0x00000008, 0xcb, 6, PutAll },
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{ "BBR0", 0x00000000, 0x0F, 0, PutBitBranch },
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{ "BBR1", 0x00000000, 0x1F, 0, PutBitBranch },
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{ "BBR2", 0x00000000, 0x2F, 0, PutBitBranch },
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{ "BBR3", 0x00000000, 0x3F, 0, PutBitBranch },
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{ "BBR4", 0x00000000, 0x4F, 0, PutBitBranch },
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{ "BBR5", 0x00000000, 0x5F, 0, PutBitBranch },
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{ "BBR6", 0x00000000, 0x6F, 0, PutBitBranch },
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{ "BBR7", 0x00000000, 0x7F, 0, PutBitBranch },
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{ "BBS0", 0x00000000, 0x8F, 0, PutBitBranch },
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{ "BBS1", 0x00000000, 0x9F, 0, PutBitBranch },
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{ "BBS2", 0x00000000, 0xAF, 0, PutBitBranch },
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{ "BBS3", 0x00000000, 0xBF, 0, PutBitBranch },
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{ "BBS4", 0x00000000, 0xCF, 0, PutBitBranch },
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{ "BBS5", 0x00000000, 0xDF, 0, PutBitBranch },
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{ "BBS6", 0x00000000, 0xEF, 0, PutBitBranch },
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{ "BBS7", 0x00000000, 0xFF, 0, PutBitBranch },
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{ "BCC", 0x00020000, 0x90, 0, PutPCRel8 },
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{ "BCS", 0x00020000, 0xb0, 0, PutPCRel8 },
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{ "BEQ", 0x00020000, 0xf0, 0, PutPCRel8 },
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{ "BIT", 0x00A0006C, 0x00, 2, PutAll },
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{ "BITQ", 0x0000000c, 0x20, 15, Put45GS02_Q },
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{ "BMI", 0x00020000, 0x30, 0, PutPCRel8 },
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{ "BNE", 0x00020000, 0xd0, 0, PutPCRel8 },
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{ "BPL", 0x00020000, 0x10, 0, PutPCRel8 },
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{ "BRA", 0x00020000, 0x80, 0, PutPCRel8 },
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{ "BRK", 0x00000001, 0x00, 0, PutAll },
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{ "BSR", 0x00040000, 0x63, 0, PutPCRel4510 },
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{ "BVC", 0x00020000, 0x50, 0, PutPCRel8 },
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{ "BVS", 0x00020000, 0x70, 0, PutPCRel8 },
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{ "CLC", 0x00000001, 0x18, 0, PutAll },
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{ "CLD", 0x00000001, 0xd8, 0, PutAll },
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{ "CLE", 0x00000001, 0x02, 0, PutAll },
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{ "CLI", 0x00000001, 0x58, 0, PutAll },
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{ "CLV", 0x00000001, 0xb8, 0, PutAll },
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{ "CMP", 0x4080A66C, 0xc0, 0, Put45GS02 },
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{ "CMPQ", 0x0000140C, 0xC0, 13, Put45GS02_Q },
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{ "CPX", 0x0080000C, 0xe0, 1, PutAll },
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{ "CPY", 0x0080000C, 0xc0, 1, PutAll },
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{ "CPZ", 0x0080000C, 0xd0, 1, Put4510 },
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{ "DEA", 0x00000001, 0x00, 3, PutAll }, /* == DEC */
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{ "DEC", 0x0000006F, 0x00, 3, PutAll },
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{ "DEQ", 0x800000ec, 0xc0, 14, Put45GS02_Q },
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{ "DEW", 0x00000004, 0xc3, 9, PutAll },
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{ "DEX", 0x00000001, 0xca, 0, PutAll },
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{ "DEY", 0x00000001, 0x88, 0, PutAll },
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{ "DEZ", 0x00000001, 0x3B, 0, PutAll },
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{ "EOM", 0x00000001, 0xea, 0, PutAll },
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{ "EOR", 0x4080A66C, 0x40, 0, Put45GS02 },
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{ "EORQ", 0x0000140C, 0x40, 13, Put45GS02_Q },
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{ "INA", 0x00000001, 0x00, 4, PutAll }, /* == INC */
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{ "INC", 0x0000006f, 0x00, 4, PutAll },
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{ "INQ", 0x800000ec, 0xe0, 14, Put45GS02_Q },
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{ "INW", 0x00000004, 0xe3, 9, PutAll },
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{ "INX", 0x00000001, 0xe8, 0, PutAll },
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{ "INY", 0x00000001, 0xc8, 0, PutAll },
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{ "INZ", 0x00000001, 0x1B, 0, PutAll },
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{ "JMP", 0x00010808, 0x4c, 6, PutAll },
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{ "JSR", 0x00010808, 0x20, 7, Put4510 },
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{ "LBCC", 0x00040000, 0x93, 0, PutPCRel4510 },
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{ "LBCS", 0x00040000, 0xb3, 0, PutPCRel4510 },
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{ "LBEQ", 0x00040000, 0xf3, 0, PutPCRel4510 },
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{ "LBMI", 0x00040000, 0x33, 0, PutPCRel4510 },
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{ "LBNE", 0x00040000, 0xd3, 0, PutPCRel4510 },
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{ "LBPL", 0x00040000, 0x13, 0, PutPCRel4510 },
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{ "LBRA", 0x00040000, 0x83, 0, PutPCRel4510 },
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{ "LBVC", 0x00040000, 0x53, 0, PutPCRel4510 },
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{ "LBVS", 0x00040000, 0x73, 0, PutPCRel4510 },
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{ "LDA", 0x4090A66C, 0xa0, 0, Put45GS02 },
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{ "LDQ", 0x4000140C, 0xa0, 13, Put45GS02_Q },
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{ "LDX", 0x0080030C, 0xa2, 1, PutAll },
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{ "LDY", 0x0080006C, 0xa0, 1, PutAll },
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{ "LDZ", 0x00800048, 0xa3, 1, Put4510 },
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{ "LSR", 0x0000006F, 0x42, 1, PutAll },
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{ "LSRQ", 0x800000ec, 0x40, 14, Put45GS02_Q },
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{ "MAP", 0x00000001, 0x5C, 0, PutAll },
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{ "NEG", 0x00000001, 0x42, 0, PutAll },
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{ "NOP", 0x00000001, 0xea, 0, PutAll }, /* == EOM */
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{ "ORA", 0x4080A66C, 0x00, 0, Put45GS02 },
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{ "ORQ", 0x0000140C, 0x00, 13, Put45GS02_Q },
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{ "PHA", 0x00000001, 0x48, 0, PutAll },
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{ "PHD", 0x08000008, 0xf4, 1, PutAll }, /* == PHW */
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{ "PHP", 0x00000001, 0x08, 0, PutAll },
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{ "PHW", 0x08000008, 0xf4, 1, PutAll },
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{ "PHX", 0x00000001, 0xda, 0, PutAll },
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{ "PHY", 0x00000001, 0x5a, 0, PutAll },
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{ "PHZ", 0x00000001, 0xdb, 0, PutAll },
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{ "PLA", 0x00000001, 0x68, 0, PutAll },
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{ "PLP", 0x00000001, 0x28, 0, PutAll },
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{ "PLX", 0x00000001, 0xfa, 0, PutAll },
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{ "PLY", 0x00000001, 0x7a, 0, PutAll },
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{ "PLZ", 0x00000001, 0xfb, 0, PutAll },
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{ "RMB0", 0x00000004, 0x07, 1, PutAll },
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{ "RMB1", 0x00000004, 0x17, 1, PutAll },
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{ "RMB2", 0x00000004, 0x27, 1, PutAll },
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{ "RMB3", 0x00000004, 0x37, 1, PutAll },
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{ "RMB4", 0x00000004, 0x47, 1, PutAll },
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{ "RMB5", 0x00000004, 0x57, 1, PutAll },
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{ "RMB6", 0x00000004, 0x67, 1, PutAll },
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{ "RMB7", 0x00000004, 0x77, 1, PutAll },
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{ "ROL", 0x0000006F, 0x22, 1, PutAll },
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{ "ROLQ", 0x800000ec, 0x20, 14, Put45GS02_Q },
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{ "ROR", 0x0000006F, 0x62, 1, PutAll },
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{ "RORQ", 0x800000ec, 0x60, 14, Put45GS02_Q },
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{ "ROW", 0x00000008, 0xeb, 6, PutAll },
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{ "RTI", 0x00000001, 0x40, 0, PutAll },
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{ "RTN", 0x00800000, 0x62, 1, PutAll },
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{ "RTS", 0x00000001, 0x60, 0, PutAll },
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{ "SBC", 0x4080A66C, 0xe0, 0, Put45GS02 },
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{ "SBCQ", 0x0000140C, 0xe0, 13, Put45GS02_Q },
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{ "SEC", 0x00000001, 0x38, 0, PutAll },
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{ "SED", 0x00000001, 0xf8, 0, PutAll },
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{ "SEE", 0x00000001, 0x03, 0, PutAll },
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{ "SEI", 0x00000001, 0x78, 0, PutAll },
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{ "SMB0", 0x00000004, 0x87, 1, PutAll },
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{ "SMB1", 0x00000004, 0x97, 1, PutAll },
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{ "SMB2", 0x00000004, 0xA7, 1, PutAll },
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{ "SMB3", 0x00000004, 0xB7, 1, PutAll },
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{ "SMB4", 0x00000004, 0xC7, 1, PutAll },
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{ "SMB5", 0x00000004, 0xD7, 1, PutAll },
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{ "SMB6", 0x00000004, 0xE7, 1, PutAll },
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{ "SMB7", 0x00000004, 0xF7, 1, PutAll },
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{ "STA", 0x4010A66C, 0x80, 0, Put45GS02 },
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{ "STQ", 0x0000140C, 0x80, 13, Put45GS02_Q },
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{ "STX", 0x0000030c, 0x82, 1, Put4510 },
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{ "STY", 0x0000006c, 0x80, 1, Put4510 },
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{ "STZ", 0x0000006c, 0x04, 5, PutAll },
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{ "TAB", 0x00000001, 0x5b, 0, PutAll },
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{ "TAX", 0x00000001, 0xaa, 0, PutAll },
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{ "TAY", 0x00000001, 0xa8, 0, PutAll },
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{ "TAZ", 0x00000001, 0x4b, 0, PutAll },
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{ "TBA", 0x00000001, 0x7b, 0, PutAll },
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{ "TRB", 0x0000000c, 0x10, 1, PutAll },
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{ "TSB", 0x0000000c, 0x00, 1, PutAll },
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{ "TSX", 0x00000001, 0xba, 0, PutAll },
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{ "TSY", 0x00000001, 0x0b, 0, PutAll },
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{ "TXA", 0x00000001, 0x8a, 0, PutAll },
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{ "TXS", 0x00000001, 0x9a, 0, PutAll },
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{ "TYA", 0x00000001, 0x98, 0, PutAll },
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{ "TYS", 0x00000001, 0x2b, 0, PutAll },
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{ "TZA", 0x00000001, 0x6b, 0, PutAll },
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/* END SORTED.SH */
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}
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};
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/* Instruction table for the 65816 */
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static const struct {
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unsigned Count;
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@@ -1192,6 +1362,7 @@ static const InsTable* InsTabs[CPU_COUNT] = {
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(const InsTable*) &InsTabHuC6280,
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(const InsTable*) &InsTabm740, /* Mitsubishi 740 */
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(const InsTable*) &InsTab4510,
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(const InsTable*) &InsTab45GS02,
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};
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const InsTable* InsTab = (const InsTable*) &InsTab6502;
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@@ -1199,85 +1370,103 @@ const InsTable* InsTab = (const InsTable*) &InsTab6502;
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** addressing mode. (The value in the table is ORed with the base opcode)
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** NOTE: each table has one entry per addressing mode!
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*/
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static unsigned char EATab[14][AM65I_COUNT] = {
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static unsigned char EATab[16][AM65I_COUNT] = {
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{ /* Table 0 (sec, sed, seo, set, slw, sta, stp, tax, tay, tsx, txa, txs, tya) */
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0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F,
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0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01,
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0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00
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},
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{ /* Table 1 (rol, ror, stx, sty, tst) */
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0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
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0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x80, 0x00, 0x00, 0x00
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0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 2 (bit) */
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0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 3 (dec, dea) */
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0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 4 (inc) */
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0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 5 (stz) */
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0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 6 (jmp, rrf) */
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0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
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0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x90, 0x00, 0x00, 0x00
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0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 7 (jsr) */
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0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
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0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 8 */
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0x00, 0x40, 0x01, 0x41, 0x00, 0x09, 0x49, 0x00,
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0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 9 (dew, inw) */
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0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 10 (NOPs, clbX, sebX) */
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0xea, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x1c, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 11 (LAX) */
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0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
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0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
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0x00, 0x00, 0x80, 0x00, 0x00, 0x00
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0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 12 (m740: JMP) */
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0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0xb2, 0x6c, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 13 (Q) */
|
||||
0x00, 0x00, 0x05, 0x0D, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00
|
||||
},
|
||||
{ /* Table 14 (Q) */
|
||||
0x00, 0x00, 0x06, 0x0e, 0x00, 0x16, 0x1e, 0x00,
|
||||
0x00, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a
|
||||
},
|
||||
{ /* Table 15 */
|
||||
0x00, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03
|
||||
}
|
||||
};
|
||||
|
||||
/* Table to build the effective SWEET16 opcode from a base opcode and an
|
||||
@@ -1325,6 +1514,8 @@ unsigned char ExtBytes[AM65I_COUNT] = {
|
||||
2, /* Immidiate word */
|
||||
2, /* Direct, Relative short */
|
||||
1, /* Special Page */
|
||||
1, /* [Direct],z */
|
||||
0, /* Q */
|
||||
};
|
||||
|
||||
/* Table that encodes the additional bytes for each SWEET16 instruction */
|
||||
@@ -1968,9 +2159,7 @@ static void PutAll (const InsDesc* Ins)
|
||||
|
||||
|
||||
|
||||
static void Put4510 (const InsDesc* Ins)
|
||||
/* Handle all other instructions, with modifications for 4510 */
|
||||
{
|
||||
static void Emit4510 (EffAddr* A) {
|
||||
/* The 4510 uses all 256 possible opcodes, so the last ones were crammed
|
||||
** in where an opcode was still undefined. As a result, some of those
|
||||
** don't follow any rules for encoding the addressmodes. So the EATab
|
||||
@@ -1990,26 +2179,90 @@ static void Put4510 (const InsDesc* Ins)
|
||||
** $d0 -> $c2 : CPZ #$00
|
||||
** $fc -> $23 : JSR ($1234,X)
|
||||
*/
|
||||
switch (A->Opcode) {
|
||||
case 0x47:
|
||||
A->Opcode = 0x44;
|
||||
break;
|
||||
case 0x57:
|
||||
A->Opcode = 0x54;
|
||||
break;
|
||||
case 0x93:
|
||||
A->Opcode = 0x82;
|
||||
break;
|
||||
case 0x9C:
|
||||
A->Opcode = 0x8B;
|
||||
break;
|
||||
case 0x9E:
|
||||
A->Opcode = 0x9B;
|
||||
break;
|
||||
case 0xAF:
|
||||
A->Opcode = 0xAB;
|
||||
break;
|
||||
case 0xBF:
|
||||
A->Opcode = 0xBB;
|
||||
break;
|
||||
case 0xB3:
|
||||
A->Opcode = 0xE2;
|
||||
break;
|
||||
case 0xD0:
|
||||
A->Opcode = 0xC2;
|
||||
break;
|
||||
case 0xFC:
|
||||
A->Opcode = 0x23;
|
||||
break;
|
||||
default: /* Keep opcode as it is */ break;
|
||||
}
|
||||
|
||||
/* No error, output code */
|
||||
EmitCode(A);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void Put4510 (const InsDesc* Ins)
|
||||
/* Handle all other instructions, with modifications for 4510 */
|
||||
{
|
||||
EffAddr A;
|
||||
|
||||
/* Evaluate the addressing mode used */
|
||||
if (EvalEA (Ins, &A)) {
|
||||
switch (A.Opcode) {
|
||||
case 0x47: A.Opcode = 0x44; break;
|
||||
case 0x57: A.Opcode = 0x54; break;
|
||||
case 0x93: A.Opcode = 0x82; break;
|
||||
case 0x9C: A.Opcode = 0x8B; break;
|
||||
case 0x9E: A.Opcode = 0x9B; break;
|
||||
case 0xAF: A.Opcode = 0xAB; break;
|
||||
case 0xBF: A.Opcode = 0xBB; break;
|
||||
case 0xB3: A.Opcode = 0xE2; break;
|
||||
case 0xD0: A.Opcode = 0xC2; break;
|
||||
case 0xFC: A.Opcode = 0x23; break;
|
||||
default: /* Keep opcode as it is */ break;
|
||||
}
|
||||
Emit4510(&A);
|
||||
}
|
||||
}
|
||||
|
||||
/* No error, output code */
|
||||
EmitCode (&A);
|
||||
|
||||
|
||||
static void Put45GS02 (const InsDesc* Ins)
|
||||
/* Handle all other instructions, with modifications for 45GS02 */
|
||||
{
|
||||
EffAddr A;
|
||||
|
||||
if (EvalEA(Ins, &A)) {
|
||||
if (A.AddrModeSet == AM65_32BIT_BASE_IND_Z) {
|
||||
Emit0(0xEA); /* NOP prefix */
|
||||
}
|
||||
Emit4510(&A);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void Put45GS02_Q (const InsDesc* Ins) {
|
||||
EffAddr A;
|
||||
|
||||
if (EvalEA(Ins, &A)) {
|
||||
Emit0(0x42);
|
||||
Emit0(0x42);
|
||||
if ((A.AddrModeBit == AM65_DIR_IND_LONG) || (A.AddrModeBit == AM65_32BIT_BASE_IND_Z)) {
|
||||
Emit0(0xEA); /* NOP prefix */
|
||||
}
|
||||
if (A.Opcode == 0xea) {
|
||||
A.Opcode = 0x1a;
|
||||
}
|
||||
else if (A.Opcode == 0xca) {
|
||||
A.Opcode = 0x3a;
|
||||
}
|
||||
EmitCode(&A);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user