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Merge branch 'master' into c_sp

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This commit is contained in:
Gorilla Sapiens
2025-06-22 19:02:24 +00:00
parent 5a4b11e7ff 7573272836
commit a7af49a763
93 changed files with 5626 additions and 554 deletions
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6
src/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
ifneq ($(shell echo),)
CMD_EXE = 1
endif

22
src/ca65/condasm.c
View File

@@ -414,6 +414,16 @@ void DoConditionals (void)
CalcOverallIfCond ();
break;
case TOK_IFP45GS02:
D = AllocIf (".IFP45GS02", 1);
NextTok ();
if (IfCond) {
SetIfCond (D, GetCPU() == CPU_45GS02);
}
ExpectSep ();
CalcOverallIfCond ();
break;
case TOK_IFP816:
D = AllocIf (".IFP816", 1);
NextTok ();
@@ -444,6 +454,16 @@ void DoConditionals (void)
CalcOverallIfCond ();
break;
case TOK_IFPM740:
D = AllocIf (".IFPM740", 1);
NextTok ();
if (IfCond) {
SetIfCond (D, GetCPU() == CPU_M740);
}
ExpectSep ();
CalcOverallIfCond ();
break;
case TOK_IFPSC02:
D = AllocIf (".IFPSC02", 1);
NextTok ();
@@ -497,9 +517,11 @@ int CheckConditionals (void)
case TOK_IFP02:
case TOK_IFP02X:
case TOK_IFP4510:
case TOK_IFP45GS02:
case TOK_IFP816:
case TOK_IFPC02:
case TOK_IFPDTV:
case TOK_IFPM740:
case TOK_IFPSC02:
case TOK_IFREF:
DoConditionals ();

46
src/ca65/ea65.c
View File

@@ -101,6 +101,9 @@ void GetEA (EffAddr* A)
if (TokIsSep (CurTok.Tok)) {
A->AddrModeSet = AM65_IMPLICIT;
if (GetCPU () == CPU_45GS02) {
A->AddrModeSet |= AM65_Q;
}
} else if (CurTok.Tok == TOK_HASH) {
@@ -114,6 +117,11 @@ void GetEA (EffAddr* A)
NextTok ();
A->AddrModeSet = AM65_ACCU;
} else if (CurTok.Tok == TOK_Q) {
NextTok ();
A->AddrModeSet = AM65_Q;
} else if (CurTok.Tok == IndirectEnter) {
/* One of the indirect modes */
@@ -160,8 +168,19 @@ void GetEA (EffAddr* A)
}
} else {
/* (adr) */
A->AddrModeSet = (CPU == CPU_4510) ? AM65_ABS_IND
: AM65_ABS_IND | AM65_ABS_IND_LONG | AM65_DIR_IND;
switch (CPU) {
case CPU_4510:
A->AddrModeSet = AM65_ABS_IND;
break;
case CPU_45GS02:
A->AddrModeSet = AM65_ABS_IND | AM65_DIR_IND;
break;
default:
A->AddrModeSet = AM65_ABS_IND | AM65_ABS_IND_LONG | AM65_DIR_IND;
break;
}
}
}
@@ -175,8 +194,14 @@ void GetEA (EffAddr* A)
if (CurTok.Tok == TOK_COMMA) {
/* [dir],y */
NextTok ();
Consume (TOK_Y, "'Y' expected");
A->AddrModeSet = AM65_DIR_IND_LONG_Y;
if (GetCPU () == CPU_45GS02) {
Consume (TOK_Z, "'Z' expected");
A->AddrModeSet = AM65_32BIT_BASE_IND_Z;
}
else {
Consume (TOK_Y, "'Y' expected");
A->AddrModeSet = AM65_DIR_IND_LONG_Y;
}
} else {
/* [dir] */
A->AddrModeSet = AM65_DIR_IND_LONG | AM65_ABS_IND_LONG;
@@ -186,10 +211,11 @@ void GetEA (EffAddr* A)
/* Remaining stuff:
**
** adr
** adr,x
** adr,y
** adr,s
** addr
** addr, x
** addr, y
** addr, s
** addr, relative addr
*/
A->Expr = Expression ();
@@ -214,7 +240,9 @@ void GetEA (EffAddr* A)
break;
default:
Error ("Syntax error");
/* FIXME: syntax error if not zp, ind */
A->AddrModeSet = AM65_ZP_REL;
break;
}

581
src/ca65/instr.c
View File

@@ -85,6 +85,12 @@ static void PutBlockTransfer (const InsDesc* Ins);
static void PutBitBranch (const InsDesc* Ins);
/* Handle 65C02 branch on bit condition */
static void PutBitBranch_m740 (const InsDesc* Ins);
/* Handle m740 branch on bit condition */
static void PutLDM_m740 (const InsDesc* Ins);
/* Handle m740 LDM instruction */
static void PutREP (const InsDesc* Ins);
/* Emit a REP instruction, track register sizes */
@@ -132,6 +138,11 @@ static void PutJSR816 (const InsDesc* Ins);
** Allowing the long_jsr_jmp_rts feature to permit a long JSR.
*/
static void PutJSR_m740 (const InsDesc* Ins);
/* Handle the JSR instruction for the m740
** Allowing the special page feature.
*/
static void PutRTS (const InsDesc* Ins attribute ((unused)));
/* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if
** the enclosing scope is FAR, but only if the long_jsr_jmp_rts feature applies.
@@ -143,6 +154,12 @@ static void PutAll (const InsDesc* Ins);
static void Put4510 (const InsDesc* Ins);
/* Handle instructions of 4510 not matching any EATab */
static void Put45GS02 (const InsDesc* Ins);
/* Handle [adr],z instructions of 45GS02 */
static void Put45GS02_Q (const InsDesc* Ins);
/* Handle Q instructions of 45GS02 */
static void PutSweet16 (const InsDesc* Ins);
/* Handle a generic sweet16 instruction */
@@ -747,6 +764,170 @@ static const struct {
}
};
/* Instruction table for the 45GS02 */
static const struct {
unsigned Count;
InsDesc Ins[149];
} InsTab45GS02 = {
/* CAUTION: table must be sorted for bsearch */
sizeof (InsTab45GS02.Ins) / sizeof (InsTab45GS02.Ins[0]),
{
/* BEGIN SORTED.SH */
{ "ADC", 0x4080A66C, 0x60, 0, Put45GS02 },
{ "ADCQ", 0x0000140C, 0x60, 13, Put45GS02_Q },
{ "AND", 0x4080A66C, 0x20, 0, Put45GS02 },
{ "ANDQ", 0x0000140C, 0x20, 13, Put45GS02_Q },
{ "ASL", 0x0000006e, 0x02, 1, PutAll },
{ "ASLQ", 0x800000ee, 0x00, 14, Put45GS02_Q },
{ "ASR", 0x00000026, 0x43, 0, Put4510 },
{ "ASRQ", 0x80000026, 0x40, 15, Put45GS02_Q },
{ "ASW", 0x00000008, 0xcb, 6, PutAll },
{ "BBR0", 0x00000000, 0x0F, 0, PutBitBranch },
{ "BBR1", 0x00000000, 0x1F, 0, PutBitBranch },
{ "BBR2", 0x00000000, 0x2F, 0, PutBitBranch },
{ "BBR3", 0x00000000, 0x3F, 0, PutBitBranch },
{ "BBR4", 0x00000000, 0x4F, 0, PutBitBranch },
{ "BBR5", 0x00000000, 0x5F, 0, PutBitBranch },
{ "BBR6", 0x00000000, 0x6F, 0, PutBitBranch },
{ "BBR7", 0x00000000, 0x7F, 0, PutBitBranch },
{ "BBS0", 0x00000000, 0x8F, 0, PutBitBranch },
{ "BBS1", 0x00000000, 0x9F, 0, PutBitBranch },
{ "BBS2", 0x00000000, 0xAF, 0, PutBitBranch },
{ "BBS3", 0x00000000, 0xBF, 0, PutBitBranch },
{ "BBS4", 0x00000000, 0xCF, 0, PutBitBranch },
{ "BBS5", 0x00000000, 0xDF, 0, PutBitBranch },
{ "BBS6", 0x00000000, 0xEF, 0, PutBitBranch },
{ "BBS7", 0x00000000, 0xFF, 0, PutBitBranch },
{ "BCC", 0x00020000, 0x90, 0, PutPCRel8 },
{ "BCS", 0x00020000, 0xb0, 0, PutPCRel8 },
{ "BEQ", 0x00020000, 0xf0, 0, PutPCRel8 },
{ "BIT", 0x00A0006C, 0x00, 2, PutAll },
{ "BITQ", 0x0000000c, 0x20, 15, Put45GS02_Q },
{ "BMI", 0x00020000, 0x30, 0, PutPCRel8 },
{ "BNE", 0x00020000, 0xd0, 0, PutPCRel8 },
{ "BPL", 0x00020000, 0x10, 0, PutPCRel8 },
{ "BRA", 0x00020000, 0x80, 0, PutPCRel8 },
{ "BRK", 0x00000001, 0x00, 0, PutAll },
{ "BSR", 0x00040000, 0x63, 0, PutPCRel4510 },
{ "BVC", 0x00020000, 0x50, 0, PutPCRel8 },
{ "BVS", 0x00020000, 0x70, 0, PutPCRel8 },
{ "CLC", 0x00000001, 0x18, 0, PutAll },
{ "CLD", 0x00000001, 0xd8, 0, PutAll },
{ "CLE", 0x00000001, 0x02, 0, PutAll },
{ "CLI", 0x00000001, 0x58, 0, PutAll },
{ "CLV", 0x00000001, 0xb8, 0, PutAll },
{ "CMP", 0x4080A66C, 0xc0, 0, Put45GS02 },
{ "CMPQ", 0x0000140C, 0xC0, 13, Put45GS02_Q },
{ "CPX", 0x0080000C, 0xe0, 1, PutAll },
{ "CPY", 0x0080000C, 0xc0, 1, PutAll },
{ "CPZ", 0x0080000C, 0xd0, 1, Put4510 },
{ "DEA", 0x00000001, 0x00, 3, PutAll }, /* == DEC */
{ "DEC", 0x0000006F, 0x00, 3, PutAll },
{ "DEQ", 0x800000ee, 0xc0, 14, Put45GS02_Q },
{ "DEW", 0x00000004, 0xc3, 9, PutAll },
{ "DEX", 0x00000001, 0xca, 0, PutAll },
{ "DEY", 0x00000001, 0x88, 0, PutAll },
{ "DEZ", 0x00000001, 0x3B, 0, PutAll },
{ "EOM", 0x00000001, 0xea, 0, PutAll },
{ "EOR", 0x4080A66C, 0x40, 0, Put45GS02 },
{ "EORQ", 0x0000140C, 0x40, 13, Put45GS02_Q },
{ "INA", 0x00000001, 0x00, 4, PutAll }, /* == INC */
{ "INC", 0x0000006f, 0x00, 4, PutAll },
{ "INQ", 0x800000ee, 0xe0, 14, Put45GS02_Q },
{ "INW", 0x00000004, 0xe3, 9, PutAll },
{ "INX", 0x00000001, 0xe8, 0, PutAll },
{ "INY", 0x00000001, 0xc8, 0, PutAll },
{ "INZ", 0x00000001, 0x1B, 0, PutAll },
{ "JMP", 0x00010808, 0x4c, 6, PutAll },
{ "JSR", 0x00010808, 0x20, 7, Put4510 },
{ "LBCC", 0x00040000, 0x93, 0, PutPCRel4510 },
{ "LBCS", 0x00040000, 0xb3, 0, PutPCRel4510 },
{ "LBEQ", 0x00040000, 0xf3, 0, PutPCRel4510 },
{ "LBMI", 0x00040000, 0x33, 0, PutPCRel4510 },
{ "LBNE", 0x00040000, 0xd3, 0, PutPCRel4510 },
{ "LBPL", 0x00040000, 0x13, 0, PutPCRel4510 },
{ "LBRA", 0x00040000, 0x83, 0, PutPCRel4510 },
{ "LBVC", 0x00040000, 0x53, 0, PutPCRel4510 },
{ "LBVS", 0x00040000, 0x73, 0, PutPCRel4510 },
{ "LDA", 0x4090A66C, 0xa0, 0, Put45GS02 },
{ "LDQ", 0x4000140C, 0xa0, 13, Put45GS02_Q },
{ "LDX", 0x0080030C, 0xa2, 1, PutAll },
{ "LDY", 0x0080006C, 0xa0, 1, PutAll },
{ "LDZ", 0x00800048, 0xa3, 1, Put4510 },
{ "LSR", 0x0000006F, 0x42, 1, PutAll },
{ "LSRQ", 0x800000ee, 0x40, 14, Put45GS02_Q },
{ "MAP", 0x00000001, 0x5C, 0, PutAll },
{ "NEG", 0x00000001, 0x42, 0, PutAll },
{ "NOP", 0x00000001, 0xea, 0, PutAll }, /* == EOM */
{ "ORA", 0x4080A66C, 0x00, 0, Put45GS02 },
{ "ORQ", 0x0000140C, 0x00, 13, Put45GS02_Q },
{ "PHA", 0x00000001, 0x48, 0, PutAll },
{ "PHD", 0x08000008, 0xf4, 1, PutAll }, /* == PHW */
{ "PHP", 0x00000001, 0x08, 0, PutAll },
{ "PHW", 0x08000008, 0xf4, 1, PutAll },
{ "PHX", 0x00000001, 0xda, 0, PutAll },
{ "PHY", 0x00000001, 0x5a, 0, PutAll },
{ "PHZ", 0x00000001, 0xdb, 0, PutAll },
{ "PLA", 0x00000001, 0x68, 0, PutAll },
{ "PLP", 0x00000001, 0x28, 0, PutAll },
{ "PLX", 0x00000001, 0xfa, 0, PutAll },
{ "PLY", 0x00000001, 0x7a, 0, PutAll },
{ "PLZ", 0x00000001, 0xfb, 0, PutAll },
{ "RMB0", 0x00000004, 0x07, 1, PutAll },
{ "RMB1", 0x00000004, 0x17, 1, PutAll },
{ "RMB2", 0x00000004, 0x27, 1, PutAll },
{ "RMB3", 0x00000004, 0x37, 1, PutAll },
{ "RMB4", 0x00000004, 0x47, 1, PutAll },
{ "RMB5", 0x00000004, 0x57, 1, PutAll },
{ "RMB6", 0x00000004, 0x67, 1, PutAll },
{ "RMB7", 0x00000004, 0x77, 1, PutAll },
{ "ROL", 0x0000006F, 0x22, 1, PutAll },
{ "ROLQ", 0x800000ee, 0x20, 14, Put45GS02_Q },
{ "ROR", 0x0000006F, 0x62, 1, PutAll },
{ "RORQ", 0x800000ee, 0x60, 14, Put45GS02_Q },
{ "ROW", 0x00000008, 0xeb, 6, PutAll },
{ "RTI", 0x00000001, 0x40, 0, PutAll },
{ "RTN", 0x00800000, 0x62, 1, PutAll },
{ "RTS", 0x00000001, 0x60, 0, PutAll },
{ "SBC", 0x4080A66C, 0xe0, 0, Put45GS02 },
{ "SBCQ", 0x0000140C, 0xe0, 13, Put45GS02_Q },
{ "SEC", 0x00000001, 0x38, 0, PutAll },
{ "SED", 0x00000001, 0xf8, 0, PutAll },
{ "SEE", 0x00000001, 0x03, 0, PutAll },
{ "SEI", 0x00000001, 0x78, 0, PutAll },
{ "SMB0", 0x00000004, 0x87, 1, PutAll },
{ "SMB1", 0x00000004, 0x97, 1, PutAll },
{ "SMB2", 0x00000004, 0xA7, 1, PutAll },
{ "SMB3", 0x00000004, 0xB7, 1, PutAll },
{ "SMB4", 0x00000004, 0xC7, 1, PutAll },
{ "SMB5", 0x00000004, 0xD7, 1, PutAll },
{ "SMB6", 0x00000004, 0xE7, 1, PutAll },
{ "SMB7", 0x00000004, 0xF7, 1, PutAll },
{ "STA", 0x4010A66C, 0x80, 0, Put45GS02 },
{ "STQ", 0x0000140C, 0x80, 13, Put45GS02_Q },
{ "STX", 0x0000030c, 0x82, 1, Put4510 },
{ "STY", 0x0000006c, 0x80, 1, Put4510 },
{ "STZ", 0x0000006c, 0x04, 5, PutAll },
{ "TAB", 0x00000001, 0x5b, 0, PutAll },
{ "TAX", 0x00000001, 0xaa, 0, PutAll },
{ "TAY", 0x00000001, 0xa8, 0, PutAll },
{ "TAZ", 0x00000001, 0x4b, 0, PutAll },
{ "TBA", 0x00000001, 0x7b, 0, PutAll },
{ "TRB", 0x0000000c, 0x10, 1, PutAll },
{ "TSB", 0x0000000c, 0x00, 1, PutAll },
{ "TSX", 0x00000001, 0xba, 0, PutAll },
{ "TSY", 0x00000001, 0x0b, 0, PutAll },
{ "TXA", 0x00000001, 0x8a, 0, PutAll },
{ "TXS", 0x00000001, 0x9a, 0, PutAll },
{ "TYA", 0x00000001, 0x98, 0, PutAll },
{ "TYS", 0x00000001, 0x2b, 0, PutAll },
{ "TZA", 0x00000001, 0x6b, 0, PutAll },
/* END SORTED.SH */
}
};
/* Instruction table for the 65816 */
static const struct {
unsigned Count;
@@ -1047,7 +1228,126 @@ static const struct {
}
};
/* CAUTION: in the pdf $1a is dec a, and $3a is inc a - if that is really the case,
* the table below (and the handler) should be fixed and this notice removed */
/* Instruction table for the m740 CPU */
static const struct {
unsigned Count;
InsDesc Ins[106];
} InsTabm740 = {
sizeof (InsTabm740.Ins) / sizeof (InsTabm740.Ins[0]),
{
/* BEGIN SORTED.SH */
{ "ADC", 0x0080A26C, 0x60, 0, PutAll },
{ "AND", 0x0080A26C, 0x20, 0, PutAll },
{ "ASL", 0x0000006e, 0x02, 1, PutAll },
{ "BBC0", 0x10000002, 0x13, 10, PutBitBranch_m740 },
{ "BBC1", 0x10000002, 0x33, 10, PutBitBranch_m740 },
{ "BBC2", 0x10000002, 0x53, 10, PutBitBranch_m740 },
{ "BBC3", 0x10000002, 0x73, 10, PutBitBranch_m740 },
{ "BBC4", 0x10000002, 0x93, 10, PutBitBranch_m740 },
{ "BBC5", 0x10000002, 0xb3, 10, PutBitBranch_m740 },
{ "BBC6", 0x10000002, 0xd3, 10, PutBitBranch_m740 },
{ "BBC7", 0x10000002, 0xf3, 10, PutBitBranch_m740 },
{ "BBS0", 0x10000002, 0x03, 10, PutBitBranch_m740 },
{ "BBS1", 0x10000002, 0x23, 10, PutBitBranch_m740 },
{ "BBS2", 0x10000002, 0x43, 10, PutBitBranch_m740 },
{ "BBS3", 0x10000002, 0x63, 10, PutBitBranch_m740 },
{ "BBS4", 0x10000002, 0x83, 10, PutBitBranch_m740 },
{ "BBS5", 0x10000002, 0xa3, 10, PutBitBranch_m740 },
{ "BBS6", 0x10000002, 0xc3, 10, PutBitBranch_m740 },
{ "BBS7", 0x10000002, 0xe3, 10, PutBitBranch_m740 },
{ "BCC", 0x00020000, 0x90, 0, PutPCRel8 },
{ "BCS", 0x00020000, 0xb0, 0, PutPCRel8 },
{ "BEQ", 0x00020000, 0xf0, 0, PutPCRel8 },
{ "BIT", 0x0000000C, 0x00, 2, PutAll },
{ "BMI", 0x00020000, 0x30, 0, PutPCRel8 },
{ "BNE", 0x00020000, 0xd0, 0, PutPCRel8 },
{ "BPL", 0x00020000, 0x10, 0, PutPCRel8 },
{ "BRA", 0x00020000, 0x80, 0, PutPCRel8 },
{ "BRK", 0x00000001, 0x00, 0, PutAll },
{ "BVC", 0x00020000, 0x50, 0, PutPCRel8 },
{ "BVS", 0x00020000, 0x70, 0, PutPCRel8 },
{ "CLB0", 0x00000006, 0x1b, 10, PutAll },
{ "CLB1", 0x00000006, 0x3b, 10, PutAll },
{ "CLB2", 0x00000006, 0x5b, 10, PutAll },
{ "CLB3", 0x00000006, 0x7b, 10, PutAll },
{ "CLB4", 0x00000006, 0x9b, 10, PutAll },
{ "CLB5", 0x00000006, 0xbb, 10, PutAll },
{ "CLB6", 0x00000006, 0xdb, 10, PutAll },
{ "CLB7", 0x00000006, 0xfb, 10, PutAll },
{ "CLC", 0x00000001, 0x18, 0, PutAll },
{ "CLD", 0x00000001, 0xd8, 0, PutAll },
{ "CLI", 0x00000001, 0x58, 0, PutAll },
{ "CLT", 0x00000001, 0x12, 0, PutAll },
{ "CLV", 0x00000001, 0xb8, 0, PutAll },
{ "CMP", 0x0080A26C, 0xc0, 0, PutAll },
{ "COM", 0x00000004, 0x44, 1, PutAll },
{ "CPX", 0x0080000C, 0xe0, 1, PutAll },
{ "CPY", 0x0080000C, 0xc0, 1, PutAll },
{ "DEC", 0x0000006F, 0x00, 3, PutAll },
{ "DEX", 0x00000001, 0xca, 0, PutAll },
{ "DEY", 0x00000001, 0x88, 0, PutAll },
{ "EOR", 0x0080A26C, 0x40, 0, PutAll },
{ "FST", 0x00000001, 0xe2, 0, PutAll },
{ "INC", 0x0000006f, 0x00, 4, PutAll },
{ "INX", 0x00000001, 0xe8, 0, PutAll },
{ "INY", 0x00000001, 0xc8, 0, PutAll },
{ "JMP", 0x00000C08, 0x00, 12, PutAll },
{ "JSR", 0x20000408, 0x00, 0, PutJSR_m740 },
{ "LDA", 0x0080A26C, 0xa0, 0, PutAll },
{ "LDM", 0x10000000, 0x3c, 0, PutLDM_m740 },
{ "LDX", 0x0080030C, 0xa2, 1, PutAll },
{ "LDY", 0x0080006C, 0xa0, 1, PutAll },
{ "LSR", 0x0000006F, 0x42, 1, PutAll },
{ "NOP", 0x00000001, 0xea, 0, PutAll },
{ "ORA", 0x0080A26C, 0x00, 0, PutAll },
{ "PHA", 0x00000001, 0x48, 0, PutAll },
{ "PHP", 0x00000001, 0x08, 0, PutAll },
{ "PLA", 0x00000001, 0x68, 0, PutAll },
{ "PLP", 0x00000001, 0x28, 0, PutAll },
{ "RMB0", 0x00000006, 0x1b, 10, PutAll },
{ "RMB1", 0x00000006, 0x3b, 10, PutAll },
{ "RMB2", 0x00000006, 0x5b, 10, PutAll },
{ "RMB3", 0x00000006, 0x7b, 10, PutAll },
{ "RMB4", 0x00000006, 0x9b, 10, PutAll },
{ "RMB5", 0x00000006, 0xbb, 10, PutAll },
{ "RMB6", 0x00000006, 0xdb, 10, PutAll },
{ "RMB7", 0x00000006, 0xfb, 10, PutAll },
{ "ROL", 0x0000006F, 0x22, 1, PutAll },
{ "ROR", 0x0000006F, 0x62, 1, PutAll },
{ "RRF", 0x00000004, 0x82, 6, PutAll },
{ "RTI", 0x00000001, 0x40, 0, PutAll },
{ "RTS", 0x00000001, 0x60, 0, PutAll },
{ "SBC", 0x0080A26C, 0xe0, 0, PutAll },
{ "SEB0", 0x00000006, 0x0b, 10, PutAll },
{ "SEB1", 0x00000006, 0x2b, 10, PutAll },
{ "SEB2", 0x00000006, 0x4b, 10, PutAll },
{ "SEB3", 0x00000006, 0x6b, 10, PutAll },
{ "SEB4", 0x00000006, 0x8b, 10, PutAll },
{ "SEB5", 0x00000006, 0xab, 10, PutAll },
{ "SEB6", 0x00000006, 0xcb, 10, PutAll },
{ "SEB7", 0x00000006, 0xeb, 10, PutAll },
{ "SEC", 0x00000001, 0x38, 0, PutAll },
{ "SED", 0x00000001, 0xf8, 0, PutAll },
{ "SEI", 0x00000001, 0x78, 0, PutAll },
{ "SET", 0x00000001, 0x32, 0, PutAll },
{ "SLW", 0x00000001, 0xC2, 0, PutAll },
{ "STA", 0x0000A26C, 0x80, 0, PutAll },
{ "STP", 0x00000001, 0x42, 0, PutAll },
{ "STX", 0x0000010c, 0x82, 1, PutAll },
{ "STY", 0x0000002c, 0x80, 1, PutAll },
{ "TAX", 0x00000001, 0xaa, 0, PutAll },
{ "TAY", 0x00000001, 0xa8, 0, PutAll },
{ "TST", 0x00000004, 0x64, 1, PutAll },
{ "TSX", 0x00000001, 0xba, 0, PutAll },
{ "TXA", 0x00000001, 0x8a, 0, PutAll },
{ "TXS", 0x00000001, 0x9a, 0, PutAll },
{ "TYA", 0x00000001, 0x98, 0, PutAll }
/* END SORTED.SH */
}
};
/* An array with instruction tables */
static const InsTable* InsTabs[CPU_COUNT] = {
@@ -1060,87 +1360,113 @@ static const InsTable* InsTabs[CPU_COUNT] = {
(const InsTable*) &InsTab65816,
(const InsTable*) &InsTabSweet16,
(const InsTable*) &InsTabHuC6280,
0, /* Mitsubishi 740 */
(const InsTable*) &InsTabm740, /* Mitsubishi 740 */
(const InsTable*) &InsTab4510,
(const InsTable*) &InsTab45GS02,
};
const InsTable* InsTab = (const InsTable*) &InsTab6502;
/* Table to build the effective 65xx opcode from a base opcode and an
** addressing mode. (The value in the table is ORed with the base opcode)
** NOTE: each table has one entry per addressing mode!
*/
static unsigned char EATab[12][AM65I_COUNT] = {
{ /* Table 0 */
static unsigned char EATab[16][AM65I_COUNT] = {
{ /* Table 0 (sec, sed, seo, set, slw, sta, stp, tax, tay, tsx, txa, txs, tya) */
0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F,
0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01,
0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00
},
{ /* Table 1 */
{ /* Table 1 (rol, ror, stx, sty, tst, cpx, cpy) */
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x80, 0x00
0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 2 */
{ /* Table 2 (bit) */
0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 3 */
{ /* Table 3 (dec, dea) */
0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 4 */
{ /* Table 4 (inc) */
0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 5 */
{ /* Table 5 (stz) */
0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 6 */
{ /* Table 6 (jmp, rrf) */
0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x90, 0x00
0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 7 (Subroutine opcodes) */
{ /* Table 7 (jsr) */
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 8 */
0x00, 0x40, 0x01, 0x41, 0x00, 0x09, 0x49, 0x00,
0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 9 */
{ /* Table 9 (dew, inw) */
0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 10 (NOPs) */
{ /* Table 10 (NOPs, clbX, sebX) */
0xea, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x1c, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 11 (LAX) */
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
0x00, 0x00, 0x80, 0x00
0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 12 (m740: JMP) */
0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0xb2, 0x6c, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 13 (Q) */
0x00, 0x00, 0x05, 0x0D, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00
},
{ /* Table 14 (45GS02: ASLQ) */
0x0a, 0x0a, 0x06, 0x0e, 0x00, 0x16, 0x1e, 0x00,
0x00, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a
},
{ /* Table 15 (45GS02: ASRQ) */
0x03, 0x03, 0x04, 0x0c, 0x00, 0x14, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03
}
};
/* Table to build the effective SWEET16 opcode from a base opcode and an
@@ -1156,6 +1482,7 @@ static unsigned char Sweet16EATab[2][AMSW16I_COUNT] = {
};
/* Table that encodes the additional bytes for each 65xx instruction */
/* NOTE: one entry per addressing mode! */
unsigned char ExtBytes[AM65I_COUNT] = {
0, /* Implicit */
0, /* Accu */
@@ -1185,6 +1512,10 @@ unsigned char ExtBytes[AM65I_COUNT] = {
7, /* Block transfer (HuC6280) */
2, /* Absolute Indirect long */
2, /* Immidiate word */
2, /* Direct, Relative short */
1, /* Special Page */
1, /* [Direct],z */
0, /* Q */
};
/* Table that encodes the additional bytes for each SWEET16 instruction */
@@ -1361,6 +1692,20 @@ static void EmitCode (EffAddr* A)
}
static void PutLDM_m740 (const InsDesc* Ins)
{
EffAddr A;
/* Evaluate the addressing mode */
if (EvalEA (Ins, &A) == 0) {
/* An error occurred */
return;
}
Emit0 (Ins->BaseCode);
EmitByte (A.Expr);
Consume (TOK_HASH, "'#' expected");
EmitByte (Expression ());
}
static long PutImmed8 (const InsDesc* Ins)
/* Parse and emit an immediate 8 bit instruction. Return the value of the
@@ -1481,6 +1826,42 @@ static void PutBitBranch (const InsDesc* Ins)
EmitSigned (GenBranchExpr (1), 1);
}
static void PutBitBranch_m740 (const InsDesc* Ins)
/* Handle m740 branch on bit condition */
{
EffAddr A;
/* Evaluate the addressing mode used */
GetEA(&A);
/* From the possible addressing modes, remove the ones that are invalid
** for this instruction or CPU.
*/
A.AddrModeSet &= Ins->AddrMode;
/* Check if we have any adressing modes left */
if (A.AddrModeSet == 0) {
Error ("Illegal addressing mode");
return;
}
A.AddrMode = BitFind (A.AddrModeSet);
A.Opcode = Ins->BaseCode;
if (A.AddrMode == AM65I_ACCU) {
/* Accu */
Emit0 (A.Opcode);
ConsumeComma ();
EmitSigned (GenBranchExpr (2), 1);
} else if (A.AddrMode == AM65I_ZP_REL) {
/* FIXME: hacky, the comma was already consumed here */
A.Opcode += 0x04;
/* Zeropage */
Emit0 (A.Opcode);
EmitByte (A.Expr);
EmitSigned (GenBranchExpr (1), 1);
}
}
static void PutREP (const InsDesc* Ins)
@@ -1584,7 +1965,6 @@ static void PutTMAn (const InsDesc* Ins)
** an immediate argument.
*/
{
/* Emit the TMA opcode itself */
Emit0 (0x43);
/* Emit the argument, which is the opcode from the table */
@@ -1640,10 +2020,8 @@ static void PutJMP (const InsDesc* Ins)
*/
{
EffAddr A;
/* Evaluate the addressing mode used */
if (EvalEA (Ins, &A)) {
/* Check for indirect addressing */
if ((A.AddrModeBit & AM65_ABS_IND) && (CPU < CPU_65SC02) && (RelaxChecks == 0)) {
@@ -1701,6 +2079,57 @@ static void PutJSR816 (const InsDesc* Ins)
}
static void PutJSR_m740 (const InsDesc* Ins)
/* Handle a JSR instruction for m740 */
{
EffAddr A;
/* Evaluate the addressing mode used */
GetEA (&A);
/* From the possible addressing modes, remove the ones that are invalid
** for this instruction or CPU.
*/
A.AddrModeSet &= Ins->AddrMode;
/* Check if we have any adressing modes left */
if (A.AddrModeSet == 0) {
Error ("Illegal addressing mode");
return;
}
A.AddrMode = BitFind (A.AddrModeSet);
/* Build the opcode */
A.Opcode = Ins->BaseCode;
switch (A.AddrMode) {
case AM65I_DIR_IND:
A.Opcode = 0x02;
Emit1 (A.Opcode, A.Expr);
break;
case AM65I_ABS:
/* If we have an expression and it's const, get it's value */
if (A.Expr) {
long Val = -1;
if (IsConstExpr (A.Expr, &Val)) {
if ((Val & 0xff00) == 0xff00) {
/* direct page */
A.Opcode = 0x22;
Emit0 (A.Opcode);
EmitByte(GenByteExpr(A.Expr));
return;
}
}
}
A.Opcode = 0x20;
Emit2 (A.Opcode, A.Expr);
break;
default:
Internal ("Invalid Opcode 0x%02x", A.Opcode);
}
}
static void PutRTS (const InsDesc* Ins attribute ((unused)))
/* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if
@@ -1730,9 +2159,7 @@ static void PutAll (const InsDesc* Ins)
static void Put4510 (const InsDesc* Ins)
/* Handle all other instructions, with modifications for 4510 */
{
static void Emit4510 (EffAddr* A) {
/* The 4510 uses all 256 possible opcodes, so the last ones were crammed
** in where an opcode was still undefined. As a result, some of those
** don't follow any rules for encoding the addressmodes. So the EATab
@@ -1752,25 +2179,91 @@ static void Put4510 (const InsDesc* Ins)
** $d0 -> $c2 : CPZ #$00
** $fc -> $23 : JSR ($1234,X)
*/
switch (A->Opcode) {
case 0x47:
A->Opcode = 0x44;
break;
case 0x57:
A->Opcode = 0x54;
break;
case 0x93:
A->Opcode = 0x82;
break;
case 0x9C:
A->Opcode = 0x8B;
break;
case 0x9E:
A->Opcode = 0x9B;
break;
case 0xAF:
A->Opcode = 0xAB;
break;
case 0xBF:
A->Opcode = 0xBB;
break;
case 0xB3:
A->Opcode = 0xE2;
break;
case 0xD0:
A->Opcode = 0xC2;
break;
case 0xFC:
A->Opcode = 0x23;
break;
default: /* Keep opcode as it is */ break;
}
/* No error, output code */
EmitCode (A);
}
static void Put4510 (const InsDesc* Ins)
/* Handle all other instructions, with modifications for 4510 */
{
EffAddr A;
/* Evaluate the addressing mode used */
if (EvalEA (Ins, &A)) {
switch (A.Opcode) {
case 0x47: A.Opcode = 0x44; break;
case 0x57: A.Opcode = 0x54; break;
case 0x93: A.Opcode = 0x82; break;
case 0x9C: A.Opcode = 0x8B; break;
case 0x9E: A.Opcode = 0x9B; break;
case 0xAF: A.Opcode = 0xAB; break;
case 0xBF: A.Opcode = 0xBB; break;
case 0xB3: A.Opcode = 0xE2; break;
case 0xD0: A.Opcode = 0xC2; break;
case 0xFC: A.Opcode = 0x23; break;
default: /* Keep opcode as it is */ break;
}
Emit4510 (&A);
}
}
/* No error, output code */
static void Put45GS02 (const InsDesc* Ins)
/* Handle all other instructions, with modifications for 45GS02 */
{
EffAddr A;
if (EvalEA (Ins, &A)) {
if (A.AddrModeSet == AM65_32BIT_BASE_IND_Z) {
Emit0 (0xEA); /* NOP prefix */
}
Emit4510 (&A);
}
}
static void Put45GS02_Q (const InsDesc* Ins)
{
EffAddr A;
if (EvalEA (Ins, &A)) {
Emit0 (0x42);
Emit0 (0x42);
if ((A.AddrModeBit == AM65_DIR_IND_LONG) ||
(A.AddrModeBit == AM65_32BIT_BASE_IND_Z)) {
Emit0 (0xEA); /* NOP prefix */
}
if (A.Opcode == 0xea) {
A.Opcode = 0x1a;
}
else if (A.Opcode == 0xca) {
A.Opcode = 0x3a;
}
EmitCode (&A);
}
}

88
src/ca65/instr.h
View File

@@ -58,34 +58,38 @@
** When assembling for the 6502 or 65C02, all addressing modes that are not
** available on these CPUs are removed before doing any checks.
*/
#define AM65_IMPLICIT 0x00000003UL
#define AM65_ACCU 0x00000002UL
#define AM65_DIR 0x00000004UL
#define AM65_ABS 0x00000008UL
#define AM65_ABS_LONG 0x00000010UL
#define AM65_DIR_X 0x00000020UL
#define AM65_ABS_X 0x00000040UL
#define AM65_ABS_LONG_X 0x00000080UL
#define AM65_DIR_Y 0x00000100UL
#define AM65_ABS_Y 0x00000200UL
#define AM65_DIR_IND 0x00000400UL
#define AM65_ABS_IND 0x00000800UL
#define AM65_DIR_IND_LONG 0x00001000UL
#define AM65_DIR_IND_Y 0x00002000UL
#define AM65_DIR_IND_LONG_Y 0x00004000UL
#define AM65_DIR_X_IND 0x00008000UL
#define AM65_ABS_X_IND 0x00010000UL
#define AM65_REL 0x00020000UL
#define AM65_REL_LONG 0x00040000UL
#define AM65_STACK_REL 0x00080000UL
#define AM65_STACK_REL_IND_Y 0x00100000UL
#define AM65_IMPLICIT 0x00000003UL /* IMP */
#define AM65_ACCU 0x00000002UL /* A */
#define AM65_DIR 0x00000004UL /* ZP */
#define AM65_ABS 0x00000008UL /* ABS */
#define AM65_ABS_LONG 0x00000010UL /* adr */
#define AM65_DIR_X 0x00000020UL /* ZP,X */
#define AM65_ABS_X 0x00000040UL /* ABS, X */
#define AM65_ABS_LONG_X 0x00000080UL /* adr,x */
#define AM65_DIR_Y 0x00000100UL /* ZP, Y */
#define AM65_ABS_Y 0x00000200UL /* ABS, Y */
#define AM65_DIR_IND 0x00000400UL /* (ZP) or (ZP),z (4510 / 45GS02) */
#define AM65_ABS_IND 0x00000800UL /* (ABS) */
#define AM65_DIR_IND_LONG 0x00001000UL /* [ABS] (65816) */
#define AM65_DIR_IND_Y 0x00002000UL /* (ZP),y */
#define AM65_DIR_IND_LONG_Y 0x00004000UL /* [adr],y (not 45GS02) */
#define AM65_DIR_X_IND 0x00008000UL /* (ZP,x) */
#define AM65_ABS_X_IND 0x00010000UL /* (ABS,x) */
#define AM65_REL 0x00020000UL /* REL */
#define AM65_REL_LONG 0x00040000UL /* LONGREL */
#define AM65_STACK_REL 0x00080000UL /* adr,s */
#define AM65_STACK_REL_IND_Y 0x00100000UL /* (rel,s),y */
#define AM65_IMM_ACCU 0x00200000UL
#define AM65_IMM_INDEX 0x00400000UL
#define AM65_IMM_IMPLICIT 0x00800000UL
#define AM65_IMM_IMPLICIT 0x00800000UL /* IMM */
#define AM65_BLOCKMOVE 0x01000000UL
#define AM65_BLOCKXFER 0x02000000UL
#define AM65_ABS_IND_LONG 0x04000000UL
#define AM65_ABS_IND_LONG 0x04000000UL /* (adr) [dir] */
#define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */
#define AM65_ZP_REL 0x10000000UL /* ZP, REL (m740) */
#define AM65_SPECIAL_PAGE 0x20000000UL /* $FFxx (m740) */
#define AM65_32BIT_BASE_IND_Z 0x40000000UL /* LDA [$nn],Z (45GS02 only) */
#define AM65_Q 0x80000000UL /* Q (45GS02 only) */
/* Bitmask for all ZP operations that have correspondent ABS ops */
#define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
@@ -106,11 +110,39 @@
#define AM65_ALL_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD)
/* Bit numbers and count */
#define AM65I_IMM_ACCU 21
#define AM65I_IMM_INDEX 22
#define AM65I_IMM_IMPLICIT 23
#define AM65I_IMM_IMPLICIT_WORD 27
#define AM65I_COUNT 28
#define AM65I_IMPLICIT 0
#define AM65I_ACCU 1
#define AM65I_DIR 2
#define AM65I_ABS 3
#define AM65I_ABS_LONG 4
#define AM65I_DIR_X 5
#define AM65I_ABS_X 6
#define AM65I_ABS_LONG_X 7
#define AM65I_DIR_Y 8
#define AM65I_ABS_Y 9
#define AM65I_DIR_IND 10
#define AM65I_ABS_IND 11
#define AM65I_DIR_IND_LONG 12
#define AM65I_DIR_IND_Y 13
#define AM65I_DIR_IND_LONG_Y 14
#define AM65I_DIR_X_IND 15
#define AM65I_ABS_X_IND 16
#define AM65I_REL 17
#define AM65I_REL_LONG 18
#define AM65I_STACK_REL 19
#define AM65I_STACK_REL_IND_Y 20
#define AM65I_IMM_ACCU 21
#define AM65I_IMM_INDEX 22
#define AM65I_IMM_IMPLICIT 23
#define AM65I_BLOCKMOVE 24
#define AM65I_BLOCKXFER 25
#define AM65I_ABS_IND_LONG 26
#define AM65I_IMM_IMPLICIT_WORD 27
#define AM65I_ZP_REL 28
#define AM65I_SPECIAL_PAGE 29
#define AM65I_32BIT_BASE_IND_Z 30
#define AM65I_Q 31
#define AM65I_COUNT 32

22
src/ca65/pseudo.c
View File

@@ -1563,7 +1563,7 @@ static void DoP02 (void)
static void DoP02X (void)
/* Switch to 6502 CPU */
/* Switch to 6502X CPU */
{
SetCPU (CPU_6502X);
}
@@ -1594,6 +1594,14 @@ static void DoP4510 (void)
static void DoP45GS02 (void)
/* Switch to 45GS02 CPU */
{
SetCPU (CPU_45GS02);
}
static void DoPDTV (void)
/* Switch to C64DTV CPU */
{
@@ -1602,6 +1610,14 @@ static void DoPDTV (void)
static void DoPM740 (void)
/* Switch to M740 CPU */
{
SetCPU (CPU_M740);
}
static void DoPageLength (void)
/* Set the page length for the listing */
{
@@ -2143,9 +2159,11 @@ static CtrlDesc CtrlCmdTab [] = {
{ ccKeepToken, DoConditionals }, /* .IFP02 */
{ ccKeepToken, DoConditionals }, /* .IFP02X */
{ ccKeepToken, DoConditionals }, /* .IFP4510 */
{ ccKeepToken, DoConditionals }, /* .IFP45GS02 */
{ ccKeepToken, DoConditionals }, /* .IFP816 */
{ ccKeepToken, DoConditionals }, /* .IFPC02 */
{ ccKeepToken, DoConditionals }, /* .IFPDTV */
{ ccKeepToken, DoConditionals }, /* .IFPM740 */
{ ccKeepToken, DoConditionals }, /* .IFPSC02 */
{ ccKeepToken, DoConditionals }, /* .IFREF */
{ ccNone, DoImport }, /* .IMPORT */
@@ -2177,11 +2195,13 @@ static CtrlDesc CtrlCmdTab [] = {
{ ccNone, DoP02 }, /* .P02 */
{ ccNone, DoP02X }, /* .P02X */
{ ccNone, DoP4510 }, /* .P4510 */
{ ccNone, DoP45GS02 }, /* .P45GS02 */
{ ccNone, DoP816 }, /* .P816 */
{ ccNone, DoPageLength }, /* .PAGELEN, .PAGELENGTH */
{ ccNone, DoUnexpected }, /* .PARAMCOUNT */
{ ccNone, DoPC02 }, /* .PSC02 */
{ ccNone, DoPDTV }, /* .PDTV */
{ ccNone, DoPM740 }, /* .PM740 */
{ ccNone, DoPopCharmap }, /* .POPCHARMAP */
{ ccNone, DoPopCPU }, /* .POPCPU */
{ ccNone, DoPopSeg }, /* .POPSEG */

17
src/ca65/scanner.c
View File

@@ -223,9 +223,11 @@ struct DotKeyword {
{ ".IFP02", TOK_IFP02 },
{ ".IFP02X", TOK_IFP02X },
{ ".IFP4510", TOK_IFP4510 },
{ ".IFP45GS02", TOK_IFP45GS02 },
{ ".IFP816", TOK_IFP816 },
{ ".IFPC02", TOK_IFPC02 },
{ ".IFPDTV", TOK_IFPDTV },
{ ".IFPM740", TOK_IFPM740 },
{ ".IFPSC02", TOK_IFPSC02 },
{ ".IFREF", TOK_IFREF },
{ ".IMPORT", TOK_IMPORT },
@@ -262,12 +264,14 @@ struct DotKeyword {
{ ".P02", TOK_P02 },
{ ".P02X", TOK_P02X },
{ ".P4510", TOK_P4510 },
{ ".P45GS02", TOK_P45GS02 },
{ ".P816", TOK_P816 },
{ ".PAGELEN", TOK_PAGELENGTH },
{ ".PAGELENGTH", TOK_PAGELENGTH },
{ ".PARAMCOUNT", TOK_PARAMCOUNT },
{ ".PC02", TOK_PC02 },
{ ".PDTV", TOK_PDTV },
{ ".PM740", TOK_PM740 },
{ ".POPCHARMAP", TOK_POPCHARMAP },
{ ".POPCPU", TOK_POPCPU },
{ ".POPSEG", TOK_POPSEG },
@@ -1277,12 +1281,19 @@ Again:
break;
case 'S':
if ((CPU == CPU_4510) || (CPU == CPU_65816)) {
if ((CPU == CPU_4510) || (CPU == CPU_45GS02) || (CPU == CPU_65816)) {
CurTok.Tok = TOK_S;
return;
}
break;
case 'Q':
if (CPU == CPU_45GS02) {
CurTok.Tok = TOK_Q;
return;
}
break;
case 'X':
CurTok.Tok = TOK_X;
return;
@@ -1297,7 +1308,7 @@ Again:
CurTok.Tok = TOK_OVERRIDE_ZP;
return;
} else {
if (CPU == CPU_4510) {
if ((CPU == CPU_4510) || (CPU == CPU_45GS02)) {
CurTok.Tok = TOK_Z;
return;
}
@@ -1309,7 +1320,7 @@ Again:
}
break;
case 2:
if ((CPU == CPU_4510) &&
if ((CPU == CPU_4510 || CPU == CPU_45GS02) &&
(toupper (SB_AtUnchecked (&CurTok.SVal, 0)) == 'S') &&
(toupper (SB_AtUnchecked (&CurTok.SVal, 1)) == 'P')) {

9
src/ca65/symentry.c
View File

@@ -211,6 +211,8 @@ static void SymReplaceExprRefs (SymEntry* S)
void SymDef (SymEntry* S, ExprNode* Expr, unsigned char AddrSize, unsigned Flags)
/* Define a new symbol */
{
int Redef = 0; /* Flag for symbol redefinition */
if (S->Flags & SF_IMPORT) {
/* Defined symbol is marked as imported external symbol */
Error ("Symbol '%m%p' is already an import", GetSymName (S));
@@ -238,6 +240,7 @@ void SymDef (SymEntry* S, ExprNode* Expr, unsigned char AddrSize, unsigned Flags
*/
FreeExpr (S->Expr);
S->Expr = 0;
Redef = 1;
}
}
@@ -291,8 +294,10 @@ void SymDef (SymEntry* S, ExprNode* Expr, unsigned char AddrSize, unsigned Flags
}
}
/* If this is not a local symbol, remember it as the last global one */
if ((S->Flags & SF_LOCAL) == 0) {
/* If this is not a local symbol and not a redefinition for a variable
** symbol, remember it as the last global one.
*/
if ((S->Flags & SF_LOCAL) == 0 && !Redef) {
SymLast = S;
}
}

5
src/ca65/token.h
View File

@@ -68,6 +68,7 @@ typedef enum token_t {
TOK_Y, /* Y register */
TOK_Z, /* Z register */
TOK_S, /* S register */
TOK_Q, /* Q pseudo register */
TOK_REG, /* Sweet16 R.. register (in sweet16 mode) */
TOK_ASSIGN, /* := */
@@ -195,9 +196,11 @@ typedef enum token_t {
TOK_IFP02,
TOK_IFP02X,
TOK_IFP4510,
TOK_IFP45GS02,
TOK_IFP816,
TOK_IFPC02,
TOK_IFPDTV,
TOK_IFPM740,
TOK_IFPSC02,
TOK_IFREF,
TOK_IMPORT,
@@ -229,11 +232,13 @@ typedef enum token_t {
TOK_P02,
TOK_P02X,
TOK_P4510,
TOK_P45GS02,
TOK_P816,
TOK_PAGELENGTH,
TOK_PARAMCOUNT,
TOK_PC02,
TOK_PDTV,
TOK_PM740,
TOK_POPCHARMAP,
TOK_POPCPU,
TOK_POPSEG,

17
src/cc65/codeopt.c
View File

@@ -119,7 +119,8 @@ static OptFunc DOptBNegAX1 = { OptBNegAX1, "OptBNegAX1", 100, 0,
static OptFunc DOptBNegAX2 = { OptBNegAX2, "OptBNegAX2", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptBNegAX3 = { OptBNegAX3, "OptBNegAX3", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptBNegAX4 = { OptBNegAX4, "OptBNegAX4", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptBinOps = { OptBinOps, "OptBinOps", 0, 0, 0, 0, 0, 0 };
static OptFunc DOptBinOps1 = { OptBinOps1, "OptBinOps1", 0, 0, 0, 0, 0, 0 };
static OptFunc DOptBinOps2 = { OptBinOps2, "OptBinOps2", 0, 0, 0, 0, 0, 0 };
static OptFunc DOptBoolCmp = { OptBoolCmp, "OptBoolCmp", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptBoolTrans = { OptBoolTrans, "OptBoolTrans", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptBoolUnary1 = { OptBoolUnary1, "OptBoolUnary1", 40, 0, 0, 0, 0, 0 };
@@ -154,6 +155,8 @@ static OptFunc DOptJumpTarget3 = { OptJumpTarget3, "OptJumpTarget3", 100, 0,
static OptFunc DOptLoad1 = { OptLoad1, "OptLoad1", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptLoad2 = { OptLoad2, "OptLoad2", 200, 0, 0, 0, 0, 0 };
static OptFunc DOptLoad3 = { OptLoad3, "OptLoad3", 0, 0, 0, 0, 0, 0 };
static OptFunc DOptLoadStore1 = { OptLoadStore1, "OptLoadStore1", 0, 0, 0, 0, 0, 0 };
static OptFunc DOptLoadStore2 = { OptLoadStore2, "OptLoadStore2", 0, 0, 0, 0, 0, 0 };
static OptFunc DOptLoadStoreLoad= { OptLoadStoreLoad,"OptLoadStoreLoad", 0, 0, 0, 0, 0, 0 };
static OptFunc DOptLongAssign = { OptLongAssign, "OptLongAssign", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptLongCopy = { OptLongCopy, "OptLongCopy", 100, 0, 0, 0, 0, 0 };
@@ -238,7 +241,8 @@ static OptFunc* OptFuncs[] = {
&DOptBNegAX2,
&DOptBNegAX3,
&DOptBNegAX4,
&DOptBinOps,
&DOptBinOps1,
&DOptBinOps2,
&DOptBoolCmp,
&DOptBoolTrans,
&DOptBoolUnary1,
@@ -273,6 +277,8 @@ static OptFunc* OptFuncs[] = {
&DOptLoad1,
&DOptLoad2,
&DOptLoad3,
&DOptLoadStore1,
&DOptLoadStore2,
&DOptLoadStoreLoad,
&DOptLongAssign,
&DOptLongCopy,
@@ -649,6 +655,7 @@ static unsigned RunOptGroup1 (CodeSeg* S)
Changes += RunOptFunc (S, &DOptSub1, 1);
Changes += RunOptFunc (S, &DOptSub3, 1);
Changes += RunOptFunc (S, &DOptLongAssign, 1);
Changes += RunOptFunc (S, &DOptLoadStore2, 1);
Changes += RunOptFunc (S, &DOptStore4, 1);
Changes += RunOptFunc (S, &DOptStore5, 1);
Changes += RunOptFunc (S, &DOptShift1, 1);
@@ -741,9 +748,10 @@ static unsigned RunOptGroup3 (CodeSeg* S)
C += RunOptFunc (S, &DOptJumpTarget3, 1); /* After OptCondBranches2 */
C += RunOptFunc (S, &DOptUnusedLoads, 1);
C += RunOptFunc (S, &DOptUnusedStores, 1);
C += RunOptFunc (S, &DOptDupLoads, 1);
C += RunOptFunc (S, &DOptStoreLoad, 1);
C += RunOptFunc (S, &DOptLoadStoreLoad, 1);
C += RunOptFunc (S, &DOptDupLoads, 1);
C += RunOptFunc (S, &DOptLoadStore1, 1);
C += RunOptFunc (S, &DOptTransfers1, 1);
C += RunOptFunc (S, &DOptTransfers3, 1);
C += RunOptFunc (S, &DOptTransfers4, 1);
@@ -755,7 +763,8 @@ static unsigned RunOptGroup3 (CodeSeg* S)
C += RunOptFunc (S, &DOptPrecalc, 1);
C += RunOptFunc (S, &DOptShiftBack, 1);
C += RunOptFunc (S, &DOptSignExtended, 1);
C += RunOptFunc (S, &DOptBinOps, 1);
C += RunOptFunc (S, &DOptBinOps1, 1);
C += RunOptFunc (S, &DOptBinOps2, 1);
Changes += C;

45
src/cc65/coptind.c
View File

@@ -590,6 +590,49 @@ unsigned OptStoreLoad (CodeSeg* S)
unsigned OptLoadStore1 (CodeSeg* S)
/* Remove an 8 bit load followed by a store into the same location. */
{
unsigned Changes = 0;
/* Walk over the entries */
unsigned I = 0;
while (I < CS_GetEntryCount (S)) {
CodeEntry* N;
/* Get next entry */
CodeEntry* E = CS_GetEntry (S, I);
/* Check if it is a load instruction followed by a store into the
** same address.
*/
if ((E->Info & OF_LOAD) != 0 &&
(N = CS_GetNextEntry (S, I)) != 0 &&
!CE_HasLabel (N) &&
E->AM == N->AM &&
((E->OPC == OP65_LDA && N->OPC == OP65_STA) ||
(E->OPC == OP65_LDX && N->OPC == OP65_STX) ||
(E->OPC == OP65_LDY && N->OPC == OP65_STY)) &&
strcmp (E->Arg, N->Arg) == 0) {
/* Memory cell has already the correct value, remove the store */
CS_DelEntry (S, I+1);
/* Remember, we had changes */
++Changes;
}
/* Next entry */
++I;
}
/* Return the number of changes made */
return Changes;
}
unsigned OptLoadStoreLoad (CodeSeg* S)
/* Search for the sequence
**
@@ -626,7 +669,7 @@ unsigned OptLoadStoreLoad (CodeSeg* S)
strcmp (L[0]->Arg, L[2]->Arg) == 0) {
/* Remove the second load */
CS_DelEntries (S, I+2, 1);
CS_DelEntry (S, I+2);
/* Remember, we had changes */
++Changes;

3
src/cc65/coptind.h
View File

@@ -66,6 +66,9 @@ unsigned OptDupLoads (CodeSeg* S);
unsigned OptStoreLoad (CodeSeg* S);
/* Remove a store followed by a load from the same location. */
unsigned OptLoadStore1 (CodeSeg* S);
/* Remove an 8 bit load followed by a store into the same location. */
unsigned OptLoadStoreLoad (CodeSeg* S);
/* Remove a load, store followed by a reload of the same location. */

106
src/cc65/coptmisc.c
View File

@@ -582,11 +582,57 @@ unsigned OptGotoSPAdj (CodeSeg* S)
/*****************************************************************************/
/* Optimize stack load ops */
/* Optimize stack load/store ops */
/*****************************************************************************/
unsigned OptLoadStore2 (CodeSeg* S)
/* Remove 16 bit stack loads followed by a store into the same location. */
{
unsigned Changes = 0;
/* Walk over the entries */
unsigned I = 0;
while (I < CS_GetEntryCount (S)) {
CodeEntry* N;
/* Get next entry */
CodeEntry* E = CS_GetEntry (S, I);
/* Check if this is a 16 bit load followed by a store into the same
** address.
*/
if (CE_IsCallTo (E, "ldaxysp") && /* Stack load ... */
RegValIsKnown (E->RI->In.RegY) && /* ... with known offs */
(N = CS_GetNextEntry (S, I)) != 0 && /* Next insn ... */
!CE_HasLabel (N) && /* ... without label ... */
N->OPC == OP65_LDY && /* ... is LDY */
CE_IsKnownImm (N, E->RI->In.RegY-1) && /* Same offset as load */
(N = CS_GetNextEntry (S, I+1)) != 0 && /* Next insn ... */
!CE_HasLabel (N) && /* ... without label ... */
CE_IsCallTo (N, "staxysp")) { /* ... is store */
/* Found - remove it. Leave the load in place. If it's unused, it
** will get removed by later steps.
*/
CS_DelEntries (S, I+1, 2);
/* Remember, we had changes */
++Changes;
}
/* Next entry */
++I;
}
/* Return the number of changes made */
return Changes;
}
unsigned OptLoad1 (CodeSeg* S)
/* Search for a call to ldaxysp where X is not used later and replace it by
** a load of just the A register.
@@ -736,7 +782,7 @@ unsigned OptLoad2 (CodeSeg* S)
unsigned OptBinOps (CodeSeg* S)
unsigned OptBinOps1 (CodeSeg* S)
/* Search for an AND/EOR/ORA where the value of A or the operand is known and
** replace it by something simpler.
*/
@@ -902,3 +948,59 @@ unsigned OptBinOps (CodeSeg* S)
/* Return the number of changes made */
return Changes;
}
unsigned OptBinOps2 (CodeSeg* S)
/* Search for an AND/EOR/ORA for identical memory locations and replace it
** by something simpler.
*/
{
unsigned Changes = 0;
/* Walk over the entries */
unsigned I = 0;
while (I < CS_GetEntryCount (S)) {
CodeEntry* N;
/* Get next entry */
CodeEntry* E = CS_GetEntry (S, I);
/* Check if this is an 8 bit load followed by a bit operation with the
** same memory cell.
*/
if (E->OPC == OP65_LDA &&
(N = CS_GetNextEntry (S, I)) != 0 && /* Next insn ... */
!CE_HasLabel (N) && /* ... without label ... */
(N->OPC == OP65_AND || /* ... is AND/EOR/ORA ... */
N->OPC == OP65_EOR ||
N->OPC == OP65_ORA) &&
E->AM == N->AM && /* ... with same addr mode ... */
strcmp (E->Arg, N->Arg) == 0) { /* ... and same argument */
/* For an EOR, the result is zero. For the other instructions, the
** result doesn't change so they can be removed.
*/
if (N->OPC == OP65_EOR) {
/* Simply insert a load of the now known value. The flags will
** be correct because of the load and the preceeding
** instructions will be removed by later steps.
*/
CodeEntry* X = NewCodeEntry (OP65_LDA, AM65_IMM, "$00", 0, N->LI);
CS_InsertEntry (S, X, I+2);
} else {
CS_DelEntry (S, I+1);
}
/* Remember, we had changes */
++Changes;
}
/* Next entry */
++I;
}
/* Return the number of changes made */
return Changes;
}

10
src/cc65/coptmisc.h
View File

@@ -99,6 +99,9 @@ unsigned OptStackPtrOps (CodeSeg* S);
unsigned OptGotoSPAdj (CodeSeg* S);
/* Optimize SP adjustment for forward 'goto' */
unsigned OptLoadStore2 (CodeSeg* S);
/* Remove 16 bit stack loads followed by a store into the same location. */
unsigned OptLoad1 (CodeSeg* S);
/* Search for a call to ldaxysp where X is not used later and replace it by
** a load of just the A register.
@@ -107,11 +110,16 @@ unsigned OptLoad1 (CodeSeg* S);
unsigned OptLoad2 (CodeSeg* S);
/* Replace calls to ldaxysp by inline code */
unsigned OptBinOps (CodeSeg* S);
unsigned OptBinOps1 (CodeSeg* S);
/* Search for an AND/EOR/ORA where the value of A or the operand is known and
** replace it by something simpler.
*/
unsigned OptBinOps2 (CodeSeg* S);
/* Search for an AND/EOR/ORA for identical memory locations and replace it
** by something simpler.
*/
/* End of coptmisc.h */

6
src/cl65/main.c
View File

@@ -1715,10 +1715,14 @@ int main (int argc, char* argv [])
/* Link the given files if requested and if we have any */
if (DoLink && LD65.FileCount > 0) {
/*
** Link() may not return if there's an error, so we install
** RemoveTempFiles() as an atexit() handler.
*/
atexit (RemoveTempFiles);
Link ();
}
RemoveTempFiles ();
if (OutputDirectory != NULL) {
xfree(OutputDirectory);
}

2
src/common/cpu.c
View File

@@ -63,6 +63,7 @@ const char* CPUNames[CPU_COUNT] = {
"huc6280",
"m740",
"4510",
"45GS02"
};
/* Tables with CPU instruction sets */
@@ -78,6 +79,7 @@ const unsigned CPUIsets[CPU_COUNT] = {
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_HUC6280,
CPU_ISET_6502 | CPU_ISET_M740,
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_4510,
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_4510 | CPU_ISET_45GS02,
};

2
src/common/cpu.h
View File

@@ -58,6 +58,7 @@ typedef enum {
CPU_HUC6280, /* Used in PC engine */
CPU_M740, /* Mitsubishi 740 series MCUs */
CPU_4510, /* CPU of C65 */
CPU_45GS02, /* CPU of MEGA65 */
CPU_COUNT /* Number of different CPUs */
} cpu_t;
@@ -74,6 +75,7 @@ enum {
CPU_ISET_HUC6280 = 1 << CPU_HUC6280,
CPU_ISET_M740 = 1 << CPU_M740,
CPU_ISET_4510 = 1 << CPU_4510,
CPU_ISET_45GS02 = 1 << CPU_45GS02
};
/* CPU used */

4
src/da65.vcxproj
View File

@@ -94,6 +94,7 @@
<ClCompile Include="da65\labels.c" />
<ClCompile Include="da65\main.c" />
<ClCompile Include="da65\opc4510.c" />
<ClCompile Include="da65\opc45GS02.c" />
<ClCompile Include="da65\opc6502.c" />
<ClCompile Include="da65\opc6502x.c" />
<ClCompile Include="da65\opc6502dtv.c" />
@@ -119,6 +120,7 @@
<ClInclude Include="da65\infofile.h" />
<ClInclude Include="da65\labels.h" />
<ClInclude Include="da65\opc4510.h" />
<ClInclude Include="da65\opc45GS02.h" />
<ClInclude Include="da65\opc6502.h" />
<ClInclude Include="da65\opc6502x.h" />
<ClInclude Include="da65\opc6502dtv.h" />
@@ -136,4 +138,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
</Project>
</Project>

3
src/da65/attrtab.c
View File

@@ -146,8 +146,7 @@ unsigned GetGranularity (attr_t Style)
case atAddrTab: return 2;
case atRtsTab: return 2;
case atTextTab: return 1;
case atSkip:
case atSkip: return 1;
default:
Internal ("GetGranularity called for style = %d", Style);
return 0;

200
src/da65/handler.c
View File

@@ -47,6 +47,7 @@
#include "handler.h"
#include "labels.h"
#include "opctable.h"
#include "opc45GS02.h"
#include "output.h"
@@ -226,6 +227,82 @@ void OH_Implicit (const OpcDesc* D)
void OH_Implicit_ea_45GS02 (const OpcDesc* D)
/* handle disassembling EOM prefixed opcodes, $ea $xx */
{
/* Get byte after EOM */
unsigned opc = GetCodeByte (PC+1);
static const char *mnemonics[8] = {
"ora", "and", "eor", "adc", "sta", "lda", "cmp", "sbc"
};
if ((opc & 0x1f) == 0x12) {
unsigned zp = GetCodeByte (PC+2);
Indent (MCol);
Output ("%s", mnemonics[(opc >> 5) & 7]);
Indent (ACol);
Output ("[$%02X],z", zp);
/* Add the code stuff as comment */
LineComment (PC, 3);
/* End the line */
LineFeed ();
} else {
OH_Implicit (D);
}
}
void OH_Implicit_42_45GS02 (const OpcDesc* D)
/* handle disassembling NEG NEG prefixed opcodes, $42 42 ($ea) $xx */
{
/* Get bytes after NEG */
unsigned n1 = GetCodeByte (PC+1);
unsigned opc = GetCodeByte (PC+2);
/* NEG:NEG:NOP (42 42 ea) prefix */
static const char *mnemonics[8] = {
"orq", "andq", "eorq", "adcq", "stq", "ldq", "cmpq", "sbcq"
};
if (n1 == 0x42) {
/* detected 0x42 0x42 */
if (opc == 0xea) {
/* detected 0x42 0x42 0xea */
unsigned opc = GetCodeByte (PC+3);
if ((opc & 0x1f) == 0x12) {
unsigned zp = GetCodeByte (PC+4);
Indent (MCol);
Output ("%s", mnemonics[(opc >> 5) & 7]);
Indent (ACol);
Output ("[$%02X]", zp); /* with or without ,z ? */
/* Add the code stuff as comment */
LineComment (PC, 5);
/* End the line */
LineFeed ();
return;
}
} else {
/* use another table for these */
const OpcDesc* NewDesc = &OpcTable_45GS02_extended[opc];
NewDesc->Handler (NewDesc);
return;
}
}
/* no prefix detected */
OH_Implicit (D);
}
void OH_Immediate (const OpcDesc* D)
{
OneLine (D, "#$%02X", GetCodeByte (PC+1));
@@ -276,6 +353,20 @@ void OH_Direct (const OpcDesc* D)
void OH_Direct_Q (const OpcDesc* D)
{
/* Get the operand */
unsigned Addr = GetCodeByte (PC+3);
/* Generate a label in pass 1 */
GenerateLabel (D->Flags, Addr);
/* Output the line */
OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
}
void OH_DirectX (const OpcDesc* D)
{
/* Get the operand */
@@ -290,6 +381,20 @@ void OH_DirectX (const OpcDesc* D)
void OH_DirectX_Q (const OpcDesc* D)
{
/* Get the operand */
unsigned Addr = GetCodeByte (PC+3);
/* Generate a label in pass 1 */
GenerateLabel (D->Flags, Addr);
/* Output the line */
OneLine (D, "%s,x", GetAddrArg (D->Flags, Addr));
}
void OH_DirectY (const OpcDesc* D)
{
/* Get the operand */
@@ -318,6 +423,20 @@ void OH_Absolute (const OpcDesc* D)
void OH_Absolute_Q (const OpcDesc* D)
{
/* Get the operand */
unsigned Addr = GetCodeWord (PC+3);
/* Generate a label in pass 1 */
GenerateLabel (D->Flags, Addr);
/* Output the line */
OneLine (D, "%s%s", GetAbsOverride (D->Flags, Addr), GetAddrArg (D->Flags, Addr));
}
void OH_AbsoluteX (const OpcDesc* D)
{
/* Get the operand */
@@ -332,6 +451,20 @@ void OH_AbsoluteX (const OpcDesc* D)
void OH_AbsoluteX_Q (const OpcDesc* D)
{
/* Get the operand */
unsigned Addr = GetCodeWord (PC+3);
/* Generate a label in pass 1 */
GenerateLabel (D->Flags, Addr);
/* Output the line */
OneLine (D, "%s%s,x", GetAbsOverride (D->Flags, Addr), GetAddrArg (D->Flags, Addr));
}
void OH_AbsoluteY (const OpcDesc* D)
{
/* Get the operand */
@@ -472,6 +605,20 @@ void OH_DirectIndirectZ (const OpcDesc* D)
void OH_DirectIndirectZ_Q (const OpcDesc* D)
{
/* Get the operand */
unsigned Addr = GetCodeByte (PC+3);
/* Generate a label in pass 1 */
GenerateLabel (D->Flags, Addr);
/* Output the line */
OneLine (D, "(%s),z", GetAddrArg (D->Flags, Addr));
}
void OH_DirectXIndirect (const OpcDesc* D)
{
/* Get the operand */
@@ -533,6 +680,26 @@ void OH_BitBranch (const OpcDesc* D)
void OH_BitBranch_m740 (const OpcDesc* D)
/* <bit> zp, rel
** NOTE: currently <bit> is part of the instruction
*/
{
/* unsigned Bit = GetCodeByte (PC) >> 5; */
unsigned Addr = GetCodeByte (PC+1);
signed char BranchOffs = GetCodeByte (PC+2);
/* Calculate the target address for the branch */
unsigned BranchAddr = (((int) PC+3) + BranchOffs) & 0xFFFF;
/* Generate a label in pass 1 */
GenerateLabel (D->Flags, Addr);
GenerateLabel (flLabel, BranchAddr);
/* Output the line */
OneLine (D, "%s, %s", GetAddrArg (D->Flags, Addr), GetAddrArg (flLabel, BranchAddr));
}
void OH_ImmediateDirect (const OpcDesc* D)
{
/* Get the operand */
@@ -720,32 +887,36 @@ void OH_DirectImmediate (const OpcDesc* D)
void OH_ZeroPageBit (const OpcDesc* D)
/* <bit> zp
** NOTE: currently <bit> is part of the instruction
*/
{
unsigned Bit = GetCodeByte (PC) >> 5;
unsigned Addr = GetCodeByte (PC+1);
/* Generate a label in pass 1 */
GenerateLabel (D->Flags, Addr);
/* Output the line */
OneLine (D, "%01X,%s", Bit, GetAddrArg (D->Flags, Addr));
OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
}
void OH_AccumulatorBit (const OpcDesc* D)
/* <bit> A
** NOTE: currently <bit> is part of the instruction
*/
{
unsigned Bit = GetCodeByte (PC) >> 5;
/* Output the line */
OneLine (D, "%01X,a", Bit);
OneLine (D, "a");
}
void OH_AccumulatorBitBranch (const OpcDesc* D)
/* <bit> A, rel
** NOTE: currently <bit> is part of the instruction
*/
{
unsigned Bit = GetCodeByte (PC) >> 5;
signed char BranchOffs = GetCodeByte (PC+1);
/* Calculate the target address for the branch */
@@ -755,7 +926,7 @@ void OH_AccumulatorBitBranch (const OpcDesc* D)
GenerateLabel (flLabel, BranchAddr);
/* Output the line */
OneLine (D, "%01X,a,%s", Bit, GetAddrArg (flLabel, BranchAddr));
OneLine (D, "a, %s", GetAddrArg (flLabel, BranchAddr));
}
@@ -770,17 +941,16 @@ void OH_JmpDirectIndirect (const OpcDesc* D)
}
void OH_SpecialPage (const OpcDesc* D)
/* m740 "special page" address mode */
{
/* Get the operand */
unsigned Addr = 0xFF00 + GetCodeByte (PC+1);
/* Get the operand */
unsigned Addr = 0xFF00 + GetCodeByte (PC+1);
/* Generate a label in pass 1 */
GenerateLabel (D->Flags, Addr);
/* Generate a label in pass 1 */
GenerateLabel (D->Flags, Addr);
/* OneLine (D, "$FF%02X", (CodeByte (PC+1)); */
OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
}

10
src/da65/handler.h
View File

@@ -78,6 +78,7 @@ void OH_DirectXIndirect (const OpcDesc*);
void OH_AbsoluteIndirect (const OpcDesc*);
void OH_BitBranch (const OpcDesc*);
void OH_BitBranch_m740 (const OpcDesc*);
void OH_ImmediateDirect (const OpcDesc*);
void OH_ImmediateDirectX (const OpcDesc*);
@@ -102,6 +103,15 @@ void OH_AccumulatorBitBranch (const OpcDesc*);
void OH_JmpDirectIndirect (const OpcDesc* D);
void OH_SpecialPage (const OpcDesc*);
/* 45GS02 */
void OH_Direct_Q (const OpcDesc*);
void OH_DirectIndirectZ_Q (const OpcDesc* D);
void OH_Absolute_Q (const OpcDesc* D);
void OH_AbsoluteX_Q (const OpcDesc* D);
void OH_DirectX_Q (const OpcDesc* D);
void OH_Implicit_ea_45GS02 (const OpcDesc* D);
void OH_Implicit_42_45GS02 (const OpcDesc* D);
/* Handlers for special instructions */
void OH_Rts (const OpcDesc*);
void OH_JmpAbsolute (const OpcDesc*);

57
src/da65/main.c
View File

@@ -59,6 +59,7 @@
#include "infofile.h"
#include "labels.h"
#include "opctable.h"
#include "opc45GS02.h"
#include "output.h"
#include "scanner.h"
#include "segment.h"
@@ -360,6 +361,51 @@ static void OptVersion (const char* Opt attribute ((unused)),
static unsigned HandleChangedLength(const OpcDesc* D, unsigned PC)
/* Instructions that have flSizeChanges set may use a different size than what
** the table says. This function adjusts the PC accordingly, so after this only
** the size from the table needs to be added to make up for the correct value
*/
{
if (D->Flags & flSizeChanges) {
if (CPU == CPU_45GS02) {
if (D->Handler == OH_Implicit_42_45GS02) {
if (GetCodeByte (PC+1) == 0x42) {
/* NEG:NEG prefix (0x42 0x42) */
unsigned opc = GetCodeByte (PC+2);
if (opc == 0xea) {
/* 42 42 ea */
if ((GetCodeByte (PC+3) & 0x1f) == 0x12) {
PC += 4;
}
} else {
/* 42 42 xx */
const OpcDesc* ED = &OpcTable_45GS02_extended[opc];
if (ED->Handler != OH_Illegal) {
PC += (ED->Size - 1);
}
}
}
} else if (D->Handler == OH_Implicit_ea_45GS02) {
/* NOP prefix (0xea) */
if ((GetCodeByte (PC+1) & 0x1f) == 0x12) {
PC += 2;
}
}
} else if (CPU == CPU_65816) {
if ((D->Handler == OH_Immediate65816M &&
GetAttr (PC) & atMem16) ||
(D->Handler == OH_Immediate65816X &&
GetAttr (PC) & atIdx16)) {
PC++;
}
}
}
return PC;
}
static void OneOpcode (unsigned RemainingBytes)
/* Disassemble one opcode */
{
@@ -435,6 +481,7 @@ static void OneOpcode (unsigned RemainingBytes)
++PC;
} else {
D->Handler (D);
PC = HandleChangedLength (D, PC);
PC += D->Size;
}
break;
@@ -466,14 +513,8 @@ static void OneOpcode (unsigned RemainingBytes)
}
/* Output the insn */
D->Handler (D);
if (CPU == CPU_65816 && (D->Flags & flSizeChanges)) {
if ((D->Handler == OH_Immediate65816M &&
GetAttr (PC) & atMem16) ||
(D->Handler == OH_Immediate65816X &&
GetAttr (PC) & atIdx16)) {
PC++;
}
}
PC = HandleChangedLength (D, PC);
PC += D->Size;
break;
}

565
src/da65/opc45GS02.c Normal file
View File

@@ -0,0 +1,565 @@
/*****************************************************************************/
/* */
/* opc45GS02.c */
/* */
/* 45GS10 opcode description table */
/* */
/* */
/* */
/* (C) 2003-2011, Ullrich von Bassewitz */
/* Roemerstrasse 52 */
/* D-70794 Filderstadt */
/* EMail: uz@cc65.org */
/* */
/* */
/* This software is provided 'as-is', without any expressed or implied */
/* warranty. In no event will the authors be held liable for any damages */
/* arising from the use of this software. */
/* */
/* Permission is granted to anyone to use this software for any purpose, */
/* including commercial applications, and to alter it and redistribute it */
/* freely, subject to the following restrictions: */
/* */
/* 1. The origin of this software must not be misrepresented; you must not */
/* claim that you wrote the original software. If you use this software */
/* in a product, an acknowledgment in the product documentation would be */
/* appreciated but is not required. */
/* 2. Altered source versions must be plainly marked as such, and must not */
/* be misrepresented as being the original software. */
/* 3. This notice may not be removed or altered from any source */
/* distribution. */
/* */
/*****************************************************************************/
/* da65 */
#include "handler.h"
#include "opc45GS02.h"
/*****************************************************************************/
/* Data */
/*****************************************************************************/
/* Descriptions for all compound instructions with NEG:NEG prefix (0x42 0x42) */
const OpcDesc OpcTable_45GS02_extended[256] = {
{ "", 1+2, flIllegal, OH_Illegal, }, /* $00 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $01 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $02 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $03 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $04 */
{ "orq", 2+2, flUseLabel, OH_Direct_Q }, /* $05 */
{ "aslq", 2+2, flUseLabel, OH_Direct_Q }, /* $06 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $07 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $08 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $09 */
{ "aslq", 1+2, flNone, OH_Accumulator }, /* $0a */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $0b */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $0c */
{ "orq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $0d */
{ "aslq", 3+2, flUseLabel, OH_Absolute_Q }, /* $0e */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $0f */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $10 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $11 */
{ "orq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $12 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $13 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $14 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $15 */
{ "aslq", 2+2, flUseLabel, OH_DirectX_Q }, /* $16 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $17 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $18 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $19 */
{ "inq", 1+2, flNone, OH_Accumulator }, /* $1a */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $1b */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $1c */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $1d */
{ "aslq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $1e */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $1f */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $20 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $21 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $22 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $23 */
{ "bitq", 2+2, flUseLabel, OH_Direct_Q }, /* $24 */
{ "andq", 2+2, flUseLabel, OH_Direct_Q }, /* $25 */
{ "rolq", 2+2, flUseLabel, OH_Direct_Q }, /* $26 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $27 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $28 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $29 */
{ "rolq", 1+2, flNone, OH_Accumulator }, /* $2a */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $2b */
{ "bitq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $2c */
{ "andq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $2d */
{ "rolq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $2e */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $2f */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $30 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $31 */
{ "andq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $32 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $33 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $34 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $35 */
{ "rolq", 2+2, flUseLabel, OH_DirectX_Q }, /* $36 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $37 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $38 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $39 */
{ "deq", 1+2, flNone, OH_Accumulator }, /* $3a */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $3b */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $3c */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $3d */
{ "rolq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $3e */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $3f */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $40 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $41 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $42 */
{ "asrq", 1+2, flNone, OH_Accumulator }, /* $43 */
{ "asrq", 2+2, flUseLabel, OH_Direct_Q }, /* $44 */
{ "eorq", 2+2, flUseLabel, OH_Direct_Q }, /* $45 */
{ "lsrq", 2+2, flUseLabel, OH_Direct_Q }, /* $46 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $47 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $48 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $49 */
{ "lsrq", 1+2, flNone, OH_Accumulator }, /* $4a */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $4b */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $4c */
{ "eorq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $4d */
{ "lsrq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $4e */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $4f */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $50 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $51 */
{ "eorq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $52 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $53 */
{ "asrq", 2+2, flUseLabel, OH_DirectX_Q }, /* $54 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $55 */
{ "lsrq", 2+2, flUseLabel, OH_DirectX_Q }, /* $56 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $57 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $58 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $59 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $5a */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $5b */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $5c */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $5d */
{ "lsrq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $5e */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $5f */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $60 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $61 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $62 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $63 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $64 */
{ "adcq", 2+2, flUseLabel, OH_Direct_Q }, /* $65 */
{ "rorq", 2+2, flUseLabel, OH_Direct_Q }, /* $66 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $67 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $68 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $69 */
{ "rorq", 1+2, flNone, OH_Accumulator }, /* $6a */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $6b */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $6c */
{ "adcq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $6d */
{ "rorq", 3+2, flUseLabel, OH_Absolute_Q }, /* $6e */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $6f */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $70 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $71 */
{ "adcq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $72 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $73 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $74 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $75 */
{ "rorq", 2+2, flUseLabel, OH_DirectX_Q }, /* $76 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $77 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $78 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $79 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $7a */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $7b */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $7c */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $7d */
{ "rorq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $7e */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $7f */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $80 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $81 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $82 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $83 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $84 */
{ "stq", 2+2, flUseLabel, OH_Direct_Q }, /* $85 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $86 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $87 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $88 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $89 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $8a */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $8b */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $8c */
{ "stq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $8d */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $8e */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $8f */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $90 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $91 */
{ "stq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $92 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $93 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $94 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $95 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $96 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $97 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $98 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $99 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $9a */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $9b */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $9c */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $9d */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $9e */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $9f */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $a0 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $a1 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $a2 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $a3 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $a4 */
{ "ldq", 2+2, flUseLabel, OH_Direct_Q }, /* $a5 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $a6 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $a7 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $a8 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $a9 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $aa */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $ab */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $ac */
{ "ldq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $ad */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $ae */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $af */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $b0 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $b1 */
{ "ldq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $b2 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $b3 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $b4 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $b5 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $b6 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $b7 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $b8 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $b9 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $ba */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $bb */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $bc */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $bd */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $be */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $bf */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $c0 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $c1 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $c2 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $c3 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $c4 */
{ "cmpq", 2+2, flUseLabel, OH_Direct_Q }, /* $c5 */
{ "deq", 2+2, flUseLabel, OH_Direct_Q }, /* $c6 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $c7 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $c8 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $c9 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $ca */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $cb */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $cc */
{ "cmpq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $cd */
{ "deq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $ce */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $cf */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $d0 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $d1 */
{ "cmpq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $d2 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $d3 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $d4 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $d5 */
{ "deq", 2+2, flUseLabel, OH_DirectX_Q }, /* $d6 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $d7 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $d8 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $d9 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $da */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $db */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $dc */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $dd */
{ "deq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $de */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $df */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $e0 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $e1 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $e2 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $e3 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $e4 */
{ "sbcq", 2+2, flUseLabel, OH_Direct_Q }, /* $e5 */
{ "inq", 2+2, flUseLabel, OH_Direct_Q }, /* $e6 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $e7 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $e8 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $e9 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $ea */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $eb */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $ec */
{ "sbcq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $ed */
{ "inq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $ee */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $ef */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $f0 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $f1 */
{ "sbcq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $f2 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $f3 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $f4 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $f5 */
{ "inq", 2+2, flUseLabel, OH_DirectX_Q }, /* $f6 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $f7 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $f8 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $f9 */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $fa */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $fb */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $fc */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $fd */
{ "inq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $fe */
{ "", 1+2, flIllegal, OH_Illegal, }, /* $ff */
};
const OpcDesc OpcTable_45GS02[256] = {
{ "brk", 1, flNone, OH_Implicit }, /* $00 */
{ "ora", 2, flUseLabel, OH_DirectXIndirect }, /* $01 */
{ "cle", 1, flNone, OH_Implicit }, /* $02 */
{ "see", 1, flNone, OH_Implicit }, /* $03 */
{ "tsb", 2, flUseLabel, OH_Direct }, /* $04 */
{ "ora", 2, flUseLabel, OH_Direct }, /* $05 */
{ "asl", 2, flUseLabel, OH_Direct }, /* $06 */
{ "rmb0", 2, flUseLabel, OH_Direct }, /* $07 */
{ "php", 1, flNone, OH_Implicit }, /* $08 */
{ "ora", 2, flNone, OH_Immediate }, /* $09 */
{ "asl", 1, flNone, OH_Accumulator }, /* $0a */
{ "tsy", 1, flNone, OH_Implicit }, /* $0b */
{ "tsb", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0c */
{ "ora", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0d */
{ "asl", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0e */
{ "bbr0", 3, flUseLabel, OH_BitBranch }, /* $0f */
{ "bpl", 2, flLabel, OH_Relative }, /* $10 */
{ "ora", 2, flUseLabel, OH_DirectIndirectY }, /* $11 */
{ "ora", 2, flUseLabel, OH_DirectIndirectZ }, /* $12 */
{ "lbpl", 3, flLabel, OH_RelativeLong4510 }, /* $13 */
{ "trb", 2, flUseLabel, OH_Direct }, /* $14 */
{ "ora", 2, flUseLabel, OH_DirectX }, /* $15 */
{ "asl", 2, flUseLabel, OH_DirectX }, /* $16 */
{ "rmb1", 2, flUseLabel, OH_Direct }, /* $17 */
{ "clc", 1, flNone, OH_Implicit }, /* $18 */
{ "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */
{ "inc", 1, flNone, OH_Accumulator }, /* $1a */
{ "inz", 1, flNone, OH_Implicit }, /* $1b */
{ "trb", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $1c */
{ "ora", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1d */
{ "asl", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1e */
{ "bbr1", 3, flUseLabel, OH_BitBranch }, /* $1f */
{ "jsr", 3, flLabel, OH_Absolute }, /* $20 */
{ "and", 2, flUseLabel, OH_DirectXIndirect }, /* $21 */
{ "jsr", 3, flLabel, OH_JmpAbsoluteIndirect }, /* $22 */
{ "jsr", 3, flLabel, OH_JmpAbsoluteXIndirect }, /* $23 */
{ "bit", 2, flUseLabel, OH_Direct }, /* $24 */
{ "and", 2, flUseLabel, OH_Direct }, /* $25 */
{ "rol", 2, flUseLabel, OH_Direct }, /* $26 */
{ "rmb2", 2, flUseLabel, OH_Direct }, /* $27 */
{ "plp", 1, flNone, OH_Implicit }, /* $28 */
{ "and", 2, flNone, OH_Immediate }, /* $29 */
{ "rol", 1, flNone, OH_Accumulator }, /* $2a */
{ "tys", 1, flNone, OH_Implicit }, /* $2b */
{ "bit", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2c */
{ "and", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2d */
{ "rol", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2e */
{ "bbr2", 3, flUseLabel, OH_BitBranch }, /* $2f */
{ "bmi", 2, flLabel, OH_Relative }, /* $30 */
{ "and", 2, flUseLabel, OH_DirectIndirectY }, /* $31 */
{ "and", 2, flUseLabel, OH_DirectIndirectZ }, /* $32 */
{ "lbmi", 3, flLabel, OH_RelativeLong4510 }, /* $33 */
{ "bit", 2, flUseLabel, OH_DirectX }, /* $34 */
{ "and", 2, flUseLabel, OH_DirectX }, /* $35 */
{ "rol", 2, flUseLabel, OH_DirectX }, /* $36 */
{ "rmb3", 2, flUseLabel, OH_Direct }, /* $37 */
{ "sec", 1, flNone, OH_Implicit }, /* $38 */
{ "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */
{ "dec", 1, flNone, OH_Accumulator }, /* $3a */
{ "dez", 1, flNone, OH_Implicit }, /* $3b */
{ "bit", 3, flUseLabel, OH_AbsoluteX }, /* $3c */
{ "and", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3d */
{ "rol", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3e */
{ "bbr3", 3, flUseLabel, OH_BitBranch }, /* $3f */
{ "rti", 1, flNone, OH_Rts }, /* $40 */
{ "eor", 2, flUseLabel, OH_DirectXIndirect }, /* $41 */
{ "neg", 1, flSizeChanges, OH_Implicit_42_45GS02 }, /* $42 */
{ "asr", 1, flNone, OH_Accumulator }, /* $43 */
{ "asr", 2, flUseLabel, OH_Direct }, /* $44 */
{ "eor", 2, flUseLabel, OH_Direct }, /* $45 */
{ "lsr", 2, flUseLabel, OH_Direct }, /* $46 */
{ "rmb4", 2, flUseLabel, OH_Direct }, /* $47 */
{ "pha", 1, flNone, OH_Implicit }, /* $48 */
{ "eor", 2, flNone, OH_Immediate }, /* $49 */
{ "lsr", 1, flNone, OH_Accumulator }, /* $4a */
{ "taz", 1, flNone, OH_Implicit }, /* $4b */
{ "jmp", 3, flLabel, OH_JmpAbsolute }, /* $4c */
{ "eor", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4d */
{ "lsr", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4e */
{ "bbr4", 3, flUseLabel, OH_BitBranch }, /* $4f */
{ "bvc", 2, flLabel, OH_Relative }, /* $50 */
{ "eor", 2, flUseLabel, OH_DirectIndirectY }, /* $51 */
{ "eor", 2, flUseLabel, OH_DirectIndirectZ }, /* $52 */
{ "lbvc", 3, flLabel, OH_RelativeLong4510 }, /* $53 */
{ "asr", 2, flUseLabel, OH_DirectX }, /* $54 */
{ "eor", 2, flUseLabel, OH_DirectX }, /* $55 */
{ "lsr", 2, flUseLabel, OH_DirectX }, /* $56 */
{ "rmb5", 2, flUseLabel, OH_Direct }, /* $57 */
{ "cli", 1, flNone, OH_Implicit }, /* $58 */
{ "eor", 3, flUseLabel, OH_AbsoluteY }, /* $59 */
{ "phy", 1, flNone, OH_Implicit }, /* $5a */
{ "tab", 1, flNone, OH_Implicit }, /* $5b */
{ "map", 1, flNone, OH_Implicit }, /* $5c */
{ "eor", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5d */
{ "lsr", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5e */
{ "bbr5", 3, flUseLabel, OH_BitBranch }, /* $5f */
{ "rts", 1, flNone, OH_Rts }, /* $60 */
{ "adc", 2, flUseLabel, OH_DirectXIndirect }, /* $61 */
{ "rtn", 2, flNone, OH_Immediate }, /* $62 */
{ "bsr", 3, flLabel, OH_RelativeLong4510 }, /* $63 */
{ "stz", 2, flUseLabel, OH_Direct }, /* $64 */
{ "adc", 2, flUseLabel, OH_Direct }, /* $65 */
{ "ror", 2, flUseLabel, OH_Direct }, /* $66 */
{ "rmb6", 2, flUseLabel, OH_Direct, }, /* $67 */
{ "pla", 1, flNone, OH_Implicit }, /* $68 */
{ "adc", 2, flNone, OH_Immediate }, /* $69 */
{ "ror", 1, flNone, OH_Accumulator }, /* $6a */
{ "tza", 1, flNone, OH_Implicit }, /* $6b */
{ "jmp", 3, flLabel, OH_JmpAbsoluteIndirect }, /* $6c */
{ "adc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $6d */
{ "ror", 3, flUseLabel, OH_Absolute }, /* $6e */
{ "bbr6", 3, flUseLabel, OH_BitBranch }, /* $6f */
{ "bvs", 2, flLabel, OH_Relative }, /* $70 */
{ "adc", 2, flUseLabel, OH_DirectIndirectY }, /* $71 */
{ "adc", 2, flUseLabel, OH_DirectIndirectZ }, /* $72 */
{ "lbvs", 3, flLabel, OH_RelativeLong4510 }, /* $73 */
{ "stz", 2, flUseLabel, OH_DirectX }, /* $74 */
{ "adc", 2, flUseLabel, OH_DirectX }, /* $75 */
{ "ror", 2, flUseLabel, OH_DirectX }, /* $76 */
{ "rmb7", 2, flUseLabel, OH_Direct }, /* $77 */
{ "sei", 1, flNone, OH_Implicit }, /* $78 */
{ "adc", 3, flUseLabel, OH_AbsoluteY }, /* $79 */
{ "ply", 1, flNone, OH_Implicit }, /* $7a */
{ "tba", 1, flNone, OH_Implicit }, /* $7b */
{ "jmp", 3, flLabel, OH_AbsoluteXIndirect }, /* $7c */
{ "adc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $7d */
{ "ror", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $7e */
{ "bbr7", 3, flUseLabel, OH_BitBranch }, /* $7f */
{ "bra", 2, flLabel, OH_Relative }, /* $80 */
{ "sta", 2, flUseLabel, OH_DirectXIndirect }, /* $81 */
{ "sta", 2, flNone, OH_StackRelativeIndirectY4510}, /* $82 */
{ "lbra", 3, flLabel, OH_RelativeLong4510 }, /* $83 */
{ "sty", 2, flUseLabel, OH_Direct }, /* $84 */
{ "sta", 2, flUseLabel, OH_Direct }, /* $85 */
{ "stx", 2, flUseLabel, OH_Direct }, /* $86 */
{ "smb0", 2, flUseLabel, OH_Direct }, /* $87 */
{ "dey", 1, flNone, OH_Implicit }, /* $88 */
{ "bit", 2, flNone, OH_Immediate }, /* $89 */
{ "txa", 1, flNone, OH_Implicit }, /* $8a */
{ "sty", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $8b */
{ "sty", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8c */
{ "sta", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8d */
{ "stx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8e */
{ "bbs0", 3, flUseLabel, OH_BitBranch }, /* $8f */
{ "bcc", 2, flLabel, OH_Relative }, /* $90 */
{ "sta", 2, flUseLabel, OH_DirectIndirectY }, /* $91 */
{ "sta", 2, flUseLabel, OH_DirectIndirectZ }, /* $92 */
{ "lbcc", 3, flLabel, OH_RelativeLong4510 }, /* $93 */
{ "sty", 2, flUseLabel, OH_DirectX }, /* $94 */
{ "sta", 2, flUseLabel, OH_DirectX }, /* $95 */
{ "stx", 2, flUseLabel, OH_DirectY }, /* $96 */
{ "smb1", 2, flUseLabel, OH_Direct }, /* $97 */
{ "tya", 1, flNone, OH_Implicit }, /* $98 */
{ "sta", 3, flUseLabel, OH_AbsoluteY }, /* $99 */
{ "txs", 1, flNone, OH_Implicit }, /* $9a */
{ "stx", 3, flUseLabel|flAbsOverride, OH_AbsoluteY }, /* $9b */
{ "stz", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $9c */
{ "sta", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9d */
{ "stz", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9e */
{ "bbs1", 3, flUseLabel, OH_BitBranch }, /* $9f */
{ "ldy", 2, flNone, OH_Immediate }, /* $a0 */
{ "lda", 2, flUseLabel, OH_DirectXIndirect }, /* $a1 */
{ "ldx", 2, flNone, OH_Immediate }, /* $a2 */
{ "ldz", 2, flNone, OH_Immediate }, /* $a3 */
{ "ldy", 2, flUseLabel, OH_Direct }, /* $a4 */
{ "lda", 2, flUseLabel, OH_Direct }, /* $a5 */
{ "ldx", 2, flUseLabel, OH_Direct }, /* $a6 */
{ "smb2", 2, flUseLabel, OH_Direct }, /* $a7 */
{ "tay", 1, flNone, OH_Implicit }, /* $a8 */
{ "lda", 2, flNone, OH_Immediate }, /* $a9 */
{ "tax", 1, flNone, OH_Implicit }, /* $aa */
{ "ldz", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ab */
{ "ldy", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ac */
{ "lda", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ad */
{ "ldx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ae */
{ "bbs2", 3, flUseLabel, OH_BitBranch }, /* $af */
{ "bcs", 2, flLabel, OH_Relative }, /* $b0 */
{ "lda", 2, flUseLabel, OH_DirectIndirectY }, /* $b1 */
{ "lda", 2, flUseLabel, OH_DirectIndirectZ }, /* $b2 */
{ "lbcs", 3, flLabel, OH_RelativeLong4510 }, /* $b3 */
{ "ldy", 2, flUseLabel, OH_DirectX }, /* $b4 */
{ "lda", 2, flUseLabel, OH_DirectX }, /* $b5 */
{ "ldx", 2, flUseLabel, OH_DirectY }, /* $b6 */
{ "smb3", 2, flUseLabel, OH_Direct }, /* $b7 */
{ "clv", 1, flNone, OH_Implicit }, /* $b8 */
{ "lda", 3, flUseLabel, OH_AbsoluteY }, /* $b9 */
{ "tsx", 1, flNone, OH_Implicit }, /* $ba */
{ "ldz", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bb */
{ "ldy", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bc */
{ "lda", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bd */
{ "ldx", 3, flUseLabel|flAbsOverride, OH_AbsoluteY }, /* $be */
{ "bbs3", 3, flUseLabel, OH_BitBranch }, /* $bf */
{ "cpy", 2, flNone, OH_Immediate }, /* $c0 */
{ "cmp", 2, flUseLabel, OH_DirectXIndirect }, /* $c1 */
{ "cpz", 2, flNone, OH_Immediate }, /* $c2 */
{ "dew", 2, flUseLabel, OH_Direct }, /* $c3 */
{ "cpy", 2, flUseLabel, OH_Direct }, /* $c4 */
{ "cmp", 2, flUseLabel, OH_Direct }, /* $c5 */
{ "dec", 2, flUseLabel, OH_Direct }, /* $c6 */
{ "smb4", 2, flUseLabel, OH_Direct }, /* $c7 */
{ "iny", 1, flNone, OH_Implicit }, /* $c8 */
{ "cmp", 2, flNone, OH_Immediate }, /* $c9 */
{ "dex", 1, flNone, OH_Implicit }, /* $ca */
{ "asw", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cb */
{ "cpy", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cc */
{ "cmp", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cd */
{ "dec", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ce */
{ "bbs4", 3, flUseLabel, OH_BitBranch }, /* $cf */
{ "bne", 2, flLabel, OH_Relative }, /* $d0 */
{ "cmp", 2, flUseLabel, OH_DirectIndirectY }, /* $d1 */
{ "cmp", 2, flUseLabel, OH_DirectIndirectZ }, /* $d2 */
{ "lbne", 3, flLabel, OH_RelativeLong4510 }, /* $d3 */
{ "cpz", 2, flUseLabel, OH_Direct }, /* $d4 */
{ "cmp", 2, flUseLabel, OH_DirectX }, /* $d5 */
{ "dec", 2, flUseLabel, OH_DirectX }, /* $d6 */
{ "smb5", 2, flUseLabel, OH_Direct }, /* $d7 */
{ "cld", 1, flNone, OH_Implicit }, /* $d8 */
{ "cmp", 3, flUseLabel, OH_AbsoluteY }, /* $d9 */
{ "phx", 1, flNone, OH_Implicit }, /* $da */
{ "phz", 1, flNone, OH_Implicit }, /* $db */
{ "cpz", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $dc */
{ "cmp", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $dd */
{ "dec", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $de */
{ "bbs5", 3, flUseLabel, OH_BitBranch }, /* $df */
{ "cpx", 2, flNone, OH_Immediate }, /* $e0 */
{ "sbc", 2, flUseLabel, OH_DirectXIndirect }, /* $e1 */
{ "lda", 2, flNone, OH_StackRelativeIndirectY4510}, /* $e2 */
{ "inw", 2, flUseLabel, OH_Direct }, /* $e3 */
{ "cpx", 2, flUseLabel, OH_Direct }, /* $e4 */
{ "sbc", 2, flUseLabel, OH_Direct }, /* $e5 */
{ "inc", 2, flUseLabel, OH_Direct }, /* $e6 */
{ "smb6", 2, flUseLabel, OH_Direct }, /* $e7 */
{ "inx", 1, flNone, OH_Implicit }, /* $e8 */
{ "sbc", 2, flNone, OH_Immediate }, /* $e9 */
{ "eom", 1, flSizeChanges, OH_Implicit_ea_45GS02 }, /* $ea */
{ "row", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $eb */
{ "cpx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ec */
{ "sbc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ed */
{ "inc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ee */
{ "bbs6", 3, flUseLabel, OH_BitBranch }, /* $ef */
{ "beq", 2, flLabel, OH_Relative }, /* $f0 */
{ "sbc", 2, flUseLabel, OH_DirectIndirectY }, /* $f1 */
{ "sbc", 2, flUseLabel, OH_DirectIndirectZ }, /* $f2 */
{ "lbeq", 3, flLabel, OH_RelativeLong4510 }, /* $f3 */
{ "phw", 3, flNone, OH_ImmediateWord }, /* $f4 */
{ "sbc", 2, flUseLabel, OH_DirectX }, /* $f5 */
{ "inc", 2, flUseLabel, OH_DirectX }, /* $f6 */
{ "smb7", 2, flUseLabel, OH_Direct }, /* $f7 */
{ "sed", 1, flNone, OH_Implicit }, /* $f8 */
{ "sbc", 3, flUseLabel, OH_AbsoluteY }, /* $f9 */
{ "plx", 1, flNone, OH_Implicit }, /* $fa */
{ "plz", 1, flNone, OH_Implicit }, /* $fb */
{ "phw", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $fc */
{ "sbc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $fd */
{ "inc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $fe */
{ "bbs7", 3, flUseLabel, OH_BitBranch }, /* $ff */
};

58
src/da65/opc45GS02.h Normal file
View File

@@ -0,0 +1,58 @@
/*****************************************************************************/
/* */
/* opc45GS02.h */
/* */
/* 45GS10 opcode description table */
/* */
/* */
/* */
/* (C) 2003 Ullrich von Bassewitz */
/* Roemerstrasse 52 */
/* D-70794 Filderstadt */
/* EMail: uz@cc65.org */
/* */
/* */
/* This software is provided 'as-is', without any expressed or implied */
/* warranty. In no event will the authors be held liable for any damages */
/* arising from the use of this software. */
/* */
/* Permission is granted to anyone to use this software for any purpose, */
/* including commercial applications, and to alter it and redistribute it */
/* freely, subject to the following restrictions: */
/* */
/* 1. The origin of this software must not be misrepresented; you must not */
/* claim that you wrote the original software. If you use this software */
/* in a product, an acknowledgment in the product documentation would be */
/* appreciated but is not required. */
/* 2. Altered source versions must be plainly marked as such, and must not */
/* be misrepresented as being the original software. */
/* 3. This notice may not be removed or altered from any source */
/* distribution. */
/* */
/*****************************************************************************/
#ifndef OPC45GS02_H
#define OPC45GS02_H
#include "opcdesc.h"
/*****************************************************************************/
/* Data */
/*****************************************************************************/
/* Descriptions for all opcodes */
extern const OpcDesc OpcTable_45GS02[256];
extern const OpcDesc OpcTable_45GS02_extended[256];
/* End of opc45GS02.h */
#endif

6
src/da65/opc6502x.c
View File

@@ -188,7 +188,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "dey", 1, flNone, OH_Implicit }, /* $88 */
{ "nop", 2, flNone, OH_Immediate }, /* $89 */
{ "txa", 1, flNone, OH_Implicit }, /* $8a */
{ "xaa", 2, flNone, OH_Immediate }, /* $8b */
{ "ane", 2, flNone, OH_Immediate }, /* $8b */
{ "sty", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8c */
{ "sta", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8d */
{ "stx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8e */
@@ -196,7 +196,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "bcc", 2, flLabel, OH_Relative }, /* $90 */
{ "sta", 2, flUseLabel, OH_DirectIndirectY }, /* $91 */
{ "jam", 1, flNone, OH_Implicit }, /* $92 */
{ "ahx", 2, flUseLabel, OH_DirectIndirectY }, /* $93 */
{ "sha", 2, flUseLabel, OH_DirectIndirectY }, /* $93 */
{ "sty", 2, flUseLabel, OH_DirectX }, /* $94 */
{ "sta", 2, flUseLabel, OH_DirectX }, /* $95 */
{ "stx", 2, flUseLabel, OH_DirectY }, /* $96 */
@@ -208,7 +208,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "shy", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9c */
{ "sta", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9d */
{ "shx", 3, flUseLabel, OH_AbsoluteY }, /* $9e */
{ "ahx", 3, flUseLabel, OH_AbsoluteY }, /* $9f */
{ "sha", 3, flUseLabel, OH_AbsoluteY }, /* $9f */
{ "ldy", 2, flNone, OH_Immediate }, /* $a0 */
{ "lda", 2, flUseLabel, OH_DirectXIndirect }, /* $a1 */
{ "ldx", 2, flNone, OH_Immediate }, /* $a2 */

141
src/da65/opcm740.c
View File

@@ -44,264 +44,265 @@
/* Data */
/*****************************************************************************/
/* CAUTION: in the pdf $1a is dec, and $3a is inc - if that is really the case,
* the table below should be fixed and this notice removed */
/* Descriptions for all opcodes */
const OpcDesc OpcTable_M740[256] = {
{ "brk", 1, flNone, OH_Implicit }, /* $00 */
{ "ora", 2, flUseLabel, OH_DirectXIndirect }, /* $01 */
{ "jsr", 2, flLabel, OH_JmpDirectIndirect }, /* $02 */
{ "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $03 */
{ "bbs0", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $03 */
{ "", 1, flIllegal, OH_Illegal }, /* $04 */
{ "ora", 2, flUseLabel, OH_Direct }, /* $05 */
{ "asl", 2, flUseLabel, OH_Direct }, /* $06 */
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $07 */
{ "bbs0", 3, flUseLabel, OH_BitBranch_m740 }, /* $07 */
{ "php", 1, flNone, OH_Implicit }, /* $08 */
{ "ora", 2, flNone, OH_Immediate }, /* $09 */
{ "asl", 1, flNone, OH_Accumulator }, /* $0a */
{ "seb", 1, flNone, OH_AccumulatorBit }, /* $0b */
{ "seb0", 1, flNone, OH_AccumulatorBit }, /* $0b */
{ "", 1, flIllegal, OH_Illegal, }, /* $0c */
{ "ora", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0d */
{ "asl", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0e */
{ "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $0f */
{ "seb0", 2, flUseLabel, OH_ZeroPageBit }, /* $0f */
{ "bpl", 2, flLabel, OH_Relative }, /* $10 */
{ "ora", 2, flUseLabel, OH_DirectIndirectY }, /* $11 */
{ "clt", 1, flNone, OH_Implicit }, /* $12 */
{ "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $13 */
{ "bbc0", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $13 */
{ "", 1, flIllegal, OH_Illegal }, /* $14 */
{ "ora", 2, flUseLabel, OH_DirectX }, /* $15 */
{ "asl", 2, flUseLabel, OH_DirectX }, /* $16 */
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $17 */
{ "bbc0", 3, flUseLabel, OH_BitBranch_m740 }, /* $17 */
{ "clc", 1, flNone, OH_Implicit }, /* $18 */
{ "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */
{ "dec", 1, flNone, OH_Accumulator }, /* $1a */
{ "clb", 1, flNone, OH_AccumulatorBit }, /* $1b */
{ "inc", 1, flNone, OH_Accumulator }, /* $1a */
{ "clb0", 1, flNone, OH_AccumulatorBit }, /* $1b */
{ "", 1, flIllegal, OH_Illegal }, /* $1c */
{ "ora", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1d */
{ "asl", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1e */
{ "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $1f */
{ "clb0", 2, flUseLabel, OH_ZeroPageBit }, /* $1f */
{ "jsr", 3, flLabel, OH_Absolute }, /* $20 */
{ "and", 2, flUseLabel, OH_DirectXIndirect }, /* $21 */
{ "jsr", 2, flLabel, OH_SpecialPage }, /* $22 */
{ "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $23 */
{ "bbs1", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $23 */
{ "bit", 2, flUseLabel, OH_Direct }, /* $24 */
{ "and", 2, flUseLabel, OH_Direct }, /* $25 */
{ "rol", 2, flUseLabel, OH_Direct }, /* $26 */
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $27 */
{ "bbs1", 3, flUseLabel, OH_BitBranch_m740 }, /* $27 */
{ "plp", 1, flNone, OH_Implicit }, /* $28 */
{ "and", 2, flNone, OH_Immediate }, /* $29 */
{ "rol", 1, flNone, OH_Accumulator }, /* $2a */
{ "seb", 1, flNone, OH_AccumulatorBit }, /* $2b */
{ "seb1", 1, flNone, OH_AccumulatorBit }, /* $2b */
{ "bit", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2c */
{ "and", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2d */
{ "rol", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2e */
{ "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $2f */
{ "seb1", 2, flUseLabel, OH_ZeroPageBit }, /* $2f */
{ "bmi", 2, flLabel, OH_Relative }, /* $30 */
{ "and", 2, flUseLabel, OH_DirectIndirectY }, /* $31 */
{ "set", 1, flNone, OH_Implicit }, /* $32 */
{ "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $33 */
{ "bbc1", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $33 */
{ "", 1, flIllegal, OH_Illegal }, /* $34 */
{ "and", 2, flUseLabel, OH_DirectX }, /* $35 */
{ "rol", 2, flUseLabel, OH_DirectX }, /* $36 */
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $37 */
{ "bbc1", 3, flUseLabel, OH_BitBranch_m740 }, /* $37 */
{ "sec", 1, flNone, OH_Implicit }, /* $38 */
{ "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */
{ "inc", 1, flNone, OH_Accumulator }, /* $3a */
{ "clb", 1, flNone, OH_AccumulatorBit }, /* $3b */
{ "dec", 1, flNone, OH_Accumulator }, /* $3a */
{ "clb1", 1, flNone, OH_AccumulatorBit }, /* $3b */
{ "ldm", 3, flLabel, OH_DirectImmediate }, /* $3c */
{ "and", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3d */
{ "rol", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3e */
{ "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $3f */
{ "clb1", 2, flUseLabel, OH_ZeroPageBit }, /* $3f */
{ "rti", 1, flNone, OH_Rts }, /* $40 */
{ "eor", 2, flUseLabel, OH_DirectXIndirect }, /* $41 */
{ "stp", 1, flNone, OH_Implicit }, /* $42 */
{ "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $43 */
{ "bbs2", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $43 */
{ "com", 2, flUseLabel, OH_Direct }, /* $44 */
{ "eor", 2, flUseLabel, OH_Direct }, /* $45 */
{ "lsr", 2, flUseLabel, OH_Direct }, /* $46 */
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $47 */
{ "bbs2", 3, flUseLabel, OH_BitBranch_m740 }, /* $47 */
{ "pha", 1, flNone, OH_Implicit }, /* $48 */
{ "eor", 2, flNone, OH_Immediate }, /* $49 */
{ "lsr", 1, flNone, OH_Accumulator }, /* $4a */
{ "seb", 1, flNone, OH_AccumulatorBit }, /* $4b */
{ "seb2", 1, flNone, OH_AccumulatorBit }, /* $4b */
{ "jmp", 3, flLabel, OH_JmpAbsolute }, /* $4c */
{ "eor", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4d */
{ "lsr", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4e */
{ "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $4f */
{ "seb2", 2, flUseLabel, OH_ZeroPageBit }, /* $4f */
{ "bvc", 2, flLabel, OH_Relative }, /* $50 */
{ "eor", 2, flUseLabel, OH_DirectIndirectY }, /* $51 */
{ "", 1, flIllegal, OH_Illegal }, /* $52 */
{ "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $53 */
{ "bbc2", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $53 */
{ "", 1, flIllegal, OH_Illegal }, /* $54 */
{ "eor", 2, flUseLabel, OH_DirectX }, /* $55 */
{ "lsr", 2, flUseLabel, OH_DirectX }, /* $56 */
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $57 */
{ "bbc2", 3, flUseLabel, OH_BitBranch_m740 }, /* $57 */
{ "cli", 1, flNone, OH_Implicit }, /* $58 */
{ "eor", 3, flUseLabel, OH_AbsoluteY }, /* $59 */
{ "", 1, flIllegal, OH_Illegal }, /* $5a */
{ "clb", 1, flNone, OH_AccumulatorBit }, /* $5b */
{ "clb2", 1, flNone, OH_AccumulatorBit }, /* $5b */
{ "", 1, flIllegal, OH_Illegal }, /* $5c */
{ "eor", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5d */
{ "lsr", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5e */
{ "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $5f */
{ "clb2", 2, flUseLabel, OH_ZeroPageBit }, /* $5f */
{ "rts", 1, flNone, OH_Rts }, /* $60 */
{ "adc", 2, flUseLabel, OH_DirectXIndirect }, /* $61 */
{ "mul", 2, flUseLabel, OH_DirectX }, /* $62 */
{ "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $63 */
{ "", 1, flIllegal, OH_Illegal }, /* $62 */
{ "bbs3", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $63 */
{ "tst", 2, flUseLabel, OH_Direct }, /* $64 */
{ "adc", 2, flUseLabel, OH_Direct }, /* $65 */
{ "ror", 2, flUseLabel, OH_Direct }, /* $66 */
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $67 */
{ "bbs3", 3, flUseLabel, OH_BitBranch_m740 }, /* $67 */
{ "pla", 1, flNone, OH_Implicit }, /* $68 */
{ "adc", 2, flNone, OH_Immediate }, /* $69 */
{ "ror", 1, flNone, OH_Accumulator }, /* $6a */
{ "seb", 1, flNone, OH_AccumulatorBit }, /* $6b */
{ "seb3", 1, flNone, OH_AccumulatorBit }, /* $6b */
{ "jmp", 3, flLabel, OH_JmpAbsoluteIndirect }, /* $6c */
{ "adc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $6d */
{ "ror", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $6e */
{ "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $6f */
{ "seb3", 2, flUseLabel, OH_ZeroPageBit }, /* $6f */
{ "bvs", 2, flLabel, OH_Relative }, /* $70 */
{ "adc", 2, flUseLabel, OH_DirectIndirectY }, /* $71 */
{ "", 1, flIllegal, OH_Illegal }, /* $72 */
{ "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $73 */
{ "bbc3", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $73 */
{ "", 1, flIllegal, OH_Illegal }, /* $74 */
{ "adc", 2, flUseLabel, OH_DirectX }, /* $75 */
{ "ror", 2, flUseLabel, OH_DirectX }, /* $76 */
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $77 */
{ "bbc3", 3, flUseLabel, OH_BitBranch_m740 }, /* $77 */
{ "sei", 1, flNone, OH_Implicit }, /* $78 */
{ "adc", 3, flUseLabel, OH_AbsoluteY }, /* $79 */
{ "", 1, flIllegal, OH_Illegal }, /* $7a */
{ "clb", 1, flNone, OH_AccumulatorBit }, /* $7b */
{ "clb3", 1, flNone, OH_AccumulatorBit }, /* $7b */
{ "", 1, flIllegal, OH_Illegal }, /* $7c */
{ "adc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $7d */
{ "ror", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $7e */
{ "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $7f */
{ "clb3", 2, flUseLabel, OH_ZeroPageBit }, /* $7f */
{ "bra", 2, flLabel, OH_Relative }, /* $80 */
{ "sta", 2, flUseLabel, OH_DirectXIndirect }, /* $81 */
{ "rrf", 2, flLabel, OH_Direct }, /* $82 */
{ "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $83 */
{ "bbs4", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $83 */
{ "sty", 2, flUseLabel, OH_Direct }, /* $84 */
{ "sta", 2, flUseLabel, OH_Direct }, /* $85 */
{ "stx", 2, flUseLabel, OH_Direct }, /* $86 */
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $87 */
{ "bbs4", 3, flUseLabel, OH_BitBranch_m740 }, /* $87 */
{ "dey", 1, flNone, OH_Implicit }, /* $88 */
{ "", 1, flIllegal, OH_Illegal }, /* $89 */
{ "txa", 1, flNone, OH_Implicit }, /* $8a */
{ "seb", 1, flNone, OH_AccumulatorBit }, /* $8b */
{ "seb4", 1, flNone, OH_AccumulatorBit }, /* $8b */
{ "sty", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8c */
{ "sta", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8d */
{ "stx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8e */
{ "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $8f */
{ "seb4", 2, flUseLabel, OH_ZeroPageBit }, /* $8f */
{ "bcc", 2, flLabel, OH_Relative }, /* $90 */
{ "sta", 2, flUseLabel, OH_DirectIndirectY }, /* $91 */
{ "", 1, flIllegal, OH_Illegal }, /* $92 */
{ "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $93 */
{ "bbc4", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $93 */
{ "sty", 2, flUseLabel, OH_DirectX }, /* $94 */
{ "sta", 2, flUseLabel, OH_DirectX }, /* $95 */
{ "stx", 2, flUseLabel, OH_DirectY }, /* $96 */
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $97 */
{ "bbc4", 3, flUseLabel, OH_BitBranch_m740 }, /* $97 */
{ "tya", 1, flNone, OH_Implicit }, /* $98 */
{ "sta", 3, flUseLabel, OH_AbsoluteY }, /* $99 */
{ "txs", 1, flNone, OH_Implicit }, /* $9a */
{ "clb", 1, flNone, OH_AccumulatorBit }, /* $9b */
{ "clb4", 1, flNone, OH_AccumulatorBit }, /* $9b */
{ "", 1, flIllegal, OH_Illegal }, /* $9c */
{ "sta", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9d */
{ "", 1, flIllegal, OH_Illegal }, /* $9e */
{ "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $9f */
{ "clb4", 2, flUseLabel, OH_ZeroPageBit }, /* $9f */
{ "ldy", 2, flNone, OH_Immediate }, /* $a0 */
{ "lda", 2, flUseLabel, OH_DirectXIndirect }, /* $a1 */
{ "ldx", 2, flNone, OH_Immediate }, /* $a2 */
{ "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $a3 */
{ "bbs5", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $a3 */
{ "ldy", 2, flUseLabel, OH_Direct }, /* $a4 */
{ "lda", 2, flUseLabel, OH_Direct }, /* $a5 */
{ "ldx", 2, flUseLabel, OH_Direct }, /* $a6 */
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $a7 */
{ "bbs5", 3, flUseLabel, OH_BitBranch_m740 }, /* $a7 */
{ "tay", 1, flNone, OH_Implicit }, /* $a8 */
{ "lda", 2, flNone, OH_Immediate }, /* $a9 */
{ "tax", 1, flNone, OH_Implicit }, /* $aa */
{ "seb", 1, flNone, OH_AccumulatorBit }, /* $ab */
{ "seb5", 1, flNone, OH_AccumulatorBit }, /* $ab */
{ "ldy", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ac */
{ "lda", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ad */
{ "ldx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ae */
{ "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $af */
{ "seb5", 2, flUseLabel, OH_ZeroPageBit }, /* $af */
{ "bcs", 2, flLabel, OH_Relative }, /* $b0 */
{ "lda", 2, flUseLabel, OH_DirectIndirectY }, /* $b1 */
{ "jmp", 2, flLabel, OH_JmpDirectIndirect }, /* $b2 */
{ "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $b3 */
{ "bbc5", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $b3 */
{ "ldy", 2, flUseLabel, OH_DirectX }, /* $b4 */
{ "lda", 2, flUseLabel, OH_DirectX }, /* $b5 */
{ "ldx", 2, flUseLabel, OH_DirectY }, /* $b6 */
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $b7 */
{ "bbc5", 3, flUseLabel, OH_BitBranch_m740 }, /* $b7 */
{ "clv", 1, flNone, OH_Implicit }, /* $b8 */
{ "lda", 3, flUseLabel, OH_AbsoluteY }, /* $b9 */
{ "tsx", 1, flNone, OH_Implicit }, /* $ba */
{ "clb", 1, flNone, OH_AccumulatorBit }, /* $bb */
{ "clb5", 1, flNone, OH_AccumulatorBit }, /* $bb */
{ "ldy", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bc */
{ "lda", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bd */
{ "ldx", 3, flUseLabel|flAbsOverride, OH_AbsoluteY }, /* $be */
{ "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $bf */
{ "clb5", 2, flUseLabel, OH_ZeroPageBit }, /* $bf */
{ "cpy", 2, flNone, OH_Immediate }, /* $c0 */
{ "cmp", 2, flUseLabel, OH_DirectXIndirect }, /* $c1 */
{ "wit", 1, flNone, OH_Implicit, }, /* $c2 */
{ "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $c3 */
{ "slw", 1, flNone, OH_Implicit, }, /* $c2 */
{ "bbs6", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $c3 */
{ "cpy", 2, flUseLabel, OH_Direct }, /* $c4 */
{ "cmp", 2, flUseLabel, OH_Direct }, /* $c5 */
{ "dec", 2, flUseLabel, OH_Direct }, /* $c6 */
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $c7 */
{ "bbs6", 3, flUseLabel, OH_BitBranch_m740 }, /* $c7 */
{ "iny", 1, flNone, OH_Implicit }, /* $c8 */
{ "cmp", 2, flNone, OH_Immediate }, /* $c9 */
{ "dex", 1, flNone, OH_Implicit }, /* $ca */
{ "seb", 1, flNone, OH_AccumulatorBit }, /* $cb */
{ "seb6", 1, flNone, OH_AccumulatorBit }, /* $cb */
{ "cpy", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cc */
{ "cmp", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cd */
{ "dec", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ce */
{ "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $cf */
{ "seb6", 2, flUseLabel, OH_ZeroPageBit }, /* $cf */
{ "bne", 2, flLabel, OH_Relative }, /* $d0 */
{ "cmp", 2, flUseLabel, OH_DirectIndirectY }, /* $d1 */
{ "", 1, flIllegal, OH_Illegal }, /* $d2 */
{ "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $d3 */
{ "bbc6", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $d3 */
{ "", 1, flIllegal, OH_Illegal }, /* $d4 */
{ "cmp", 2, flUseLabel, OH_DirectX }, /* $d5 */
{ "dec", 2, flUseLabel, OH_DirectX }, /* $d6 */
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $d7 */
{ "bbc6", 3, flUseLabel, OH_BitBranch_m740 }, /* $d7 */
{ "cld", 1, flNone, OH_Implicit }, /* $d8 */
{ "cmp", 3, flUseLabel, OH_AbsoluteY }, /* $d9 */
{ "", 1, flIllegal, OH_Illegal }, /* $da */
{ "clb", 1, flNone, OH_AccumulatorBit }, /* $db */
{ "clb6", 1, flNone, OH_AccumulatorBit }, /* $db */
{ "", 1, flIllegal, OH_Illegal }, /* $dc */
{ "cmp", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $dd */
{ "dec", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $de */
{ "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $df */
{ "clb6", 2, flUseLabel, OH_ZeroPageBit }, /* $df */
{ "cpx", 2, flNone, OH_Immediate }, /* $e0 */
{ "sbc", 2, flUseLabel, OH_DirectXIndirect }, /* $e1 */
{ "div", 2, flUseLabel, OH_DirectX }, /* $e2 */
{ "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $e3 */
{ "fst", 1, flNone, OH_Implicit }, /* $e2 */
{ "bbs7", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $e3 */
{ "cpx", 2, flUseLabel, OH_Direct }, /* $e4 */
{ "sbc", 2, flUseLabel, OH_Direct }, /* $e5 */
{ "inc", 2, flUseLabel, OH_Direct }, /* $e6 */
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $e7 */
{ "bbs7", 3, flUseLabel, OH_BitBranch_m740 }, /* $e7 */
{ "inx", 1, flNone, OH_Implicit }, /* $e8 */
{ "sbc", 2, flNone, OH_Immediate }, /* $e9 */
{ "nop", 1, flNone, OH_Implicit }, /* $ea */
{ "seb", 1, flNone, OH_AccumulatorBit }, /* $eb */
{ "seb7", 1, flNone, OH_AccumulatorBit }, /* $eb */
{ "cpx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ec */
{ "sbc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ed */
{ "inc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ee */
{ "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $ef */
{ "seb7", 2, flUseLabel, OH_ZeroPageBit }, /* $ef */
{ "beq", 2, flLabel, OH_Relative }, /* $f0 */
{ "sbc", 2, flUseLabel, OH_DirectIndirectY }, /* $f1 */
{ "", 1, flIllegal, OH_Illegal }, /* $f2 */
{ "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $f3 */
{ "bbc7", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $f3 */
{ "", 1, flIllegal, OH_Illegal }, /* $f4 */
{ "sbc", 2, flUseLabel, OH_DirectX }, /* $f5 */
{ "inc", 2, flUseLabel, OH_DirectX }, /* $f6 */
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $f7 */
{ "bbc7", 3, flUseLabel, OH_BitBranch_m740 }, /* $f7 */
{ "sed", 1, flNone, OH_Implicit }, /* $f8 */
{ "sbc", 3, flUseLabel, OH_AbsoluteY }, /* $f9 */
{ "", 1, flIllegal, OH_Illegal }, /* $fa */
{ "clb", 1, flNone, OH_AccumulatorBit }, /* $fb */
{ "clb7", 1, flNone, OH_AccumulatorBit }, /* $fb */
{ "", 1, flIllegal, OH_Illegal }, /* $fc */
{ "sbc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $fd */
{ "inc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $fe */
{ "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $ff */
{ "clb7", 2, flUseLabel, OH_ZeroPageBit }, /* $ff */
};

2
src/da65/opctable.c
View File

@@ -36,6 +36,7 @@
/* da65 */
#include "error.h"
#include "opc4510.h"
#include "opc45GS02.h"
#include "opc6502.h"
#include "opc6502x.h"
#include "opc6502dtv.h"
@@ -78,6 +79,7 @@ void SetOpcTable (cpu_t CPU)
case CPU_HUC6280: OpcTable = OpcTable_HuC6280; break;
case CPU_M740: OpcTable = OpcTable_M740; break;
case CPU_4510: OpcTable = OpcTable_4510; break;
case CPU_45GS02: OpcTable = OpcTable_45GS02; break;
default: Error ("Unsupported CPU");
}
}