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Redesigned GEOS VLIR linking:

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- No more post-linking with resource compiler, rather ld65 directly creates the VLIR CVT file.
- No more dynamic linker config creation, rather the built-in 'geos' config is usable both for SEQ CVT and VLIR CVT files.

ToDos:
- Have ld65 accept alignment to $FD.
- Adjust docs / samples.

git-svn-id: svn://svn.cc65.org/cc65/trunk@5314 b7a2c559-68d2-44c3-8de9-860c34a00d81
This commit is contained in:
ol.sc
2011-12-26 22:54:04 +00:00
parent 1947d15c48
commit d810ed97d2
4 changed files with 646 additions and 647 deletions
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70
src/ld65/cfg/geos.cfg
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@@ -1,22 +1,64 @@
SYMBOLS {
__STACKSIZE__: type = weak, value = $0400; # 1k stack
__STACKSIZE__: type = weak, value = $0400; # 1k stack
__OVERLAYSIZE__: type = weak, value = $0000; # no overlays by default
__OVERLAYADDR__: type = weak, value = $6000 - __OVERLAYSIZE__;
}
MEMORY {
ZP: file = "", define = yes, start = $0058, size = $0028;
HEADER: file = %O, start = $0204, size = $01FC;
RAM: file = %O, define = yes, start = $0400, size = $5C00 - __STACKSIZE__;
CVT: file = %O, start = $0, size = $80000;
ZP: define = yes, start = $58, size = $1A + $06;
VLIR0: define = yes, start = $0400, size = __OVERLAYADDR__ - __STACKSIZE__ - $0400;
VLIR1: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR2: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR3: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR4: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR5: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR6: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR7: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR8: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR9: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR10: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR11: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR12: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR13: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR14: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR15: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR16: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR17: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR18: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
VLIR19: define = yes, start = __OVERLAYADDR__, size = __OVERLAYSIZE__;
}
SEGMENTS {
HEADER: load = HEADER, type = ro;
STARTUP: load = RAM, type = ro;
LOWCODE: load = RAM, type = ro, optional = yes;
INIT: load = RAM, type = ro, define = yes, optional = yes;
CODE: load = RAM, type = ro;
RODATA: load = RAM, type = ro;
DATA: load = RAM, type = rw;
BSS: load = RAM, type = bss, define = yes;
ZEROPAGE: load = ZP, type = zp;
EXTZP: load = ZP, type = zp;
ZEROPAGE: type = zp, load = ZP;
EXTZP: type = zp, load = ZP;
DIRENTRY: type = ro, load = CVT, align = $FE;
FILEINFO: type = ro, load = CVT, align = $FE;
RECORDS: type = ro, load = CVT, align = $FE, optional = yes;
STARTUP: type = ro, run = VLIR0, load = CVT, align_load = $FE, define = yes;
LOWCODE: type = ro, run = VLIR0, load = CVT, optional = yes;
INIT: type = ro, run = VLIR0, load = CVT, define = yes, optional = yes;
CODE: type = ro, run = VLIR0, load = CVT;
RODATA: type = ro, run = VLIR0, load = CVT;
DATA: type = rw, run = VLIR0, load = CVT;
BSS: type = bss, load = VLIR0, define = yes;
OVERLAY1: type = ro, run = VLIR1, load = CVT, align_load = $FE, optional = yes;
OVERLAY2: type = ro, run = VLIR2, load = CVT, align_load = $FE, optional = yes;
OVERLAY3: type = ro, run = VLIR3, load = CVT, align_load = $FE, optional = yes;
OVERLAY4: type = ro, run = VLIR4, load = CVT, align_load = $FE, optional = yes;
OVERLAY5: type = ro, run = VLIR5, load = CVT, align_load = $FE, optional = yes;
OVERLAY6: type = ro, run = VLIR6, load = CVT, align_load = $FE, optional = yes;
OVERLAY7: type = ro, run = VLIR7, load = CVT, align_load = $FE, optional = yes;
OVERLAY8: type = ro, run = VLIR8, load = CVT, align_load = $FE, optional = yes;
OVERLAY9: type = ro, run = VLIR9, load = CVT, align_load = $FE, optional = yes;
OVERLAY10: type = ro, run = VLIR10, load = CVT, align_load = $FE, optional = yes;
OVERLAY11: type = ro, run = VLIR11, load = CVT, align_load = $FE, optional = yes;
OVERLAY12: type = ro, run = VLIR12, load = CVT, align_load = $FE, optional = yes;
OVERLAY13: type = ro, run = VLIR13, load = CVT, align_load = $FE, optional = yes;
OVERLAY14: type = ro, run = VLIR14, load = CVT, align_load = $FE, optional = yes;
OVERLAY15: type = ro, run = VLIR15, load = CVT, align_load = $FE, optional = yes;
OVERLAY16: type = ro, run = VLIR16, load = CVT, align_load = $FE, optional = yes;
OVERLAY17: type = ro, run = VLIR17, load = CVT, align_load = $FE, optional = yes;
OVERLAY18: type = ro, run = VLIR18, load = CVT, align_load = $FE, optional = yes;
OVERLAY19: type = ro, run = VLIR19, load = CVT, align_load = $FE, optional = yes;
}
FEATURES {
CONDES: segment = INIT,