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Spare cycles on IRQ path

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This commit is contained in:
Colin Leroy-Mira
2023-10-10 21:33:17 +02:00
committed by Oliver Schmidt
parent 65ce3a6792
commit e3759a3ead
1 changed files with 5 additions and 7 deletions
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12
libsrc/apple2/ser/a2.gs.s
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@@ -602,9 +602,9 @@ SER_IOCTL:
; was handled, otherwise with carry clear. ; was handled, otherwise with carry clear.
SER_IRQ: SER_IRQ:
ldx #$01 ; IRQ status is always in A reg ldy #RR_INTR_PENDING_STATUS ; IRQ status is always in A reg
ldy #RR_INTR_PENDING_STATUS sty SCCAREG
jsr readSSCReg lda SCCAREG
and CurChanIrqFlags ; Is this ours? and CurChanIrqFlags ; Is this ours?
beq Done beq Done
@@ -626,9 +626,9 @@ SER_IRQ:
CheckSpecial: CheckSpecial:
; Always check IRQ special flags from Channel B (Ref page 5-24) ; Always check IRQ special flags from Channel B (Ref page 5-24)
; X is still 0 there.
ldy #RR_IRQ_STATUS ldy #RR_IRQ_STATUS
jsr readSSCReg sty SCCBREG
lda SCCBREG
and #IRQ_MASQ and #IRQ_MASQ
cmp #IRQ_SPECIAL cmp #IRQ_SPECIAL
@@ -636,7 +636,6 @@ CheckSpecial:
; Clear exint ; Clear exint
ldx Channel ldx Channel
ldy #WR_INIT_CTRL ldy #WR_INIT_CTRL
lda #INIT_CTRL_CLEAR_EIRQ lda #INIT_CTRL_CLEAR_EIRQ
jsr writeSCCReg jsr writeSCCReg
@@ -645,7 +644,6 @@ CheckSpecial:
rts rts
Flow: ldx Channel ; Assert flow control if buffer space too low Flow: ldx Channel ; Assert flow control if buffer space too low
ldy #WR_TX_CTRL ldy #WR_TX_CTRL
lda RtsOff lda RtsOff
jsr writeSCCReg jsr writeSCCReg