bslathi19/cc65
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Mikey enumeration values for cc65 include files and new bit definitions for ca65

Browse Source
This commit is contained in:
Alex Thissen
2024-08-09 13:11:02 +02:00
committed by Alex Thissen
parent 394d3b1964
commit eb6003aaf7
2 changed files with 430 additions and 172 deletions
Download Patch File Download Diff File Expand all files Collapse all files

185
asminc/lynx.inc
View File

@@ -138,8 +138,9 @@ HOWIE = $FCC4
; *** Mikey Addresses ; *** Mikey Addresses
; *** ; ***
; Mikey Timers ; Mikey timers
; Logical timer names
TIMER0 = $FD00 TIMER0 = $FD00
TIMER1 = $FD04 TIMER1 = $FD04
TIMER2 = $FD08 TIMER2 = $FD08
@@ -148,9 +149,9 @@ TIMER4 = $FD10
TIMER5 = $FD14 TIMER5 = $FD14
TIMER6 = $FD18 TIMER6 = $FD18
TIMER7 = $FD1C TIMER7 = $FD1C
HTIMER = $FD00 ; horizontal line timer (timer 0) HTIMER = TIMER0 ; horizontal line timer (timer 0)
VTIMER = $FD08 ; vertical blank timer (timer 2) VTIMER = TIMER2 ; vertical blank timer (timer 2)
STIMER = $FD1C ; sound timer (timer 7) STIMER = TIMER7 ; sound timer (timer 7)
HTIMBKUP = $FD00 ; horizontal line timer (timer 0) HTIMBKUP = $FD00 ; horizontal line timer (timer 0)
HTIMCTLA = $FD01 HTIMCTLA = $FD01
@@ -199,6 +200,35 @@ TIM7CTLA = $FD1D
TIM7CNT = $FD1E TIM7CNT = $FD1E
TIM7CTLB = $FD1F TIM7CTLB = $FD1F
; Timer offsets
TIM_BACKUP = 0
TIM_CONTROLA = 1
TIM_COUNT = 2
TIM_CONTROLB = 3
; TIM_CONTROLA control bits
ENABLE_INT = %10000000
RESET_DONE = %01000000
ENABLE_RELOAD = %00010000
ENABLE_COUNT = %00001000
AUD_CLOCK_MASK = %00000111
; Clock settings
AUD_LINKING = %00000111
AUD_64 = %00000110
AUD_32 = %00000101
AUD_16 = %00000100
AUD_8 = %00000011
AUD_4 = %00000010
AUD_2 = %00000001
AUD_1 = %00000000
; TIM_CONTROLB control bits
TIMER_DONE = %00001000
LAST_CLOCK = %00000100
BORROW_IN = %00000010
BORROW_OUT = %00000001
; Mikey Audio ; Mikey Audio
AUDIO0 = $FD20 ; audio channel 0 AUDIO0 = $FD20 ; audio channel 0
@@ -238,85 +268,155 @@ AUD3BKUP = $FD3C
AUD3CTLA = $FD3D AUD3CTLA = $FD3D
AUD3CNT = $FD3E AUD3CNT = $FD3E
AUD3CTLB = $FD3F AUD3CTLB = $FD3F
; AUD_CONTROL bits are almost identical to TIM_CONTROLA bits.
; See TIM_CONTROLA above for the other definitions
FEEDBACK_7 = %10000000
ENABLE_INTEGRATE = %00100000
; Stereo control registers follow
; Stereo capability does not exist in all Lynxes
; Left and right may be reversed, and if so will be corrected in a later
; release
ATTENREG0 = $FD40 ; Stereo attenuation registers
ATTENREG1 = $FD41
ATTENREG2 = $FD42
ATTENREG3 = $FD43
LEFT_ATTENMASK = %11110000
RIGHT_ATTENMASK = %00001111
; Bit definitions for MPAN and MSTEREO registers
LEFT3_SELECT = %10000000
LEFT2_SELECT = %01000000
LEFT1_SELECT = %00100000
LEFT0_SELECT = %00010000
RIGHT3_SELECT = %00001000
RIGHT2_SELECT = %00000100
RIGHT1_SELECT = %00000010
RIGHT0_SELECT = %00000001
MPAN = $FD44
MSTEREO = $FD50 MSTEREO = $FD50
; Mikey Misc ; Mikey interrupts
INTRST = $FD80
INTSET = $FD81
; Interrupt bits in INTRST and INTSET ; Interrupt bits in INTRST and INTSET
TIMER0_INTERRUPT = $01 TIMER0_INTERRUPT = %00000001
TIMER1_INTERRUPT = $02 TIMER1_INTERRUPT = %00000010
TIMER2_INTERRUPT = $04 TIMER2_INTERRUPT = %00000100
TIMER3_INTERRUPT = $08 TIMER3_INTERRUPT = %00001000
TIMER4_INTERRUPT = $10 TIMER4_INTERRUPT = %00010000
TIMER5_INTERRUPT = $20 TIMER5_INTERRUPT = %00100000
TIMER6_INTERRUPT = $40 TIMER6_INTERRUPT = %01000000
TIMER7_INTERRUPT = $80 TIMER7_INTERRUPT = %10000000
HBL_INTERRUPT = TIMER0_INTERRUPT HBL_INTERRUPT = TIMER0_INTERRUPT
VBL_INTERRUPT = TIMER2_INTERRUPT VBL_INTERRUPT = TIMER2_INTERRUPT
SERIAL_INTERRUPT = TIMER4_INTERRUPT SERIAL_INTERRUPT = TIMER4_INTERRUPT
SND_INTERRUPT = TIMER7_INTERRUPT SND_INTERRUPT = TIMER7_INTERRUPT
INTRST = $FD80
INTSET = $FD81
MAGRDY0 = $FD84 MAGRDY0 = $FD84
MAGRDY1 = $FD85 MAGRDY1 = $FD85
AUDIN = $FD86 AUDIN = $FD86
SYSCTL1 = $FD87 SYSCTL1 = $FD87
; SYSCTL1 bit definitions
POWERON = %00000010
CART_ADDR_STROBE = %00000001
MIKEYHREV = $FD88 MIKEYHREV = $FD88
MIKEYSREV = $FD89 MIKEYSREV = $FD89
IODIR = $FD8A IODIR = $FD8A
IODAT = $FD8B IODAT = $FD8B
; IODIR and IODAT bit definitions ; IODIR and IODAT bit definitions
AUDIN_BIT = $10 ; Note that there is also the address AUDIN AUDIN_BIT = %00010000 ; Note that there is also the address AUDIN
READ_ENABLE = $10 ; Same bit for AUDIN_BIT READ_ENABLE = %00010000 ; Same bit for AUDIN_BIT
RESTLESS = $08 RESTLESS = %00001000
NOEXP = $04 ; If set, redeye is not connected NOEXP = %00000100 ; If set, redeye is not connected
CART_ADDR_DATA = $02 CART_ADDR_DATA = %00000010
CART_POWER_OFF = $02 ; Same bit for CART_ADDR_DATA CART_POWER_OFF = %00000010 ; Same bit for CART_ADDR_DATA
EXTERNAL_POWER = $01 EXTERNAL_POWER = %00000001
SERCTL = $FD8C SERCTL = $FD8C
; SERCTL bit definitions for write operations ; SERCTL bit definitions for write operations
TXINTEN = $80 TXINTEN = %10000000
RXINTEN = $40 RXINTEN = %01000000
PAREN = $10 PAREN = %00010000
RESETERR = $08 RESETERR = %00001000
TXOPEN = $04 TXOPEN = %00000100
TXBRK = $02 TXBRK = %00000010
PAREVEN = $01 PAREVEN = %00000001
; SERCTL bit definitions for read operations ; SERCTL bit definitions for read operations
TXRDY = $80 TXRDY = %10000000
RXRDY = $40 RXRDY = %01000000
TXEMPTY = $20 TXEMPTY = %00100000
PARERR = $10 PARERR = %00010000
OVERRUN = $08 OVERRUN = %00001000
FRAMERR = $04 FRAMERR = %00000100
RXBRK = $02 RXBRK = %00000010
PARBIT = $01 PARBIT = %00000001
SERDAT = $FD8D SERDAT = $FD8D
SDONEACK = $FD90 SDONEACK = $FD90
CPUSLEEP = $FD91 CPUSLEEP = $FD91
DISPCTL = $FD92 DISPCTL = $FD92
; DISPCTL bit definitions
DISP_COLOR = %10000000 ; must be set to 1
DISP_FOURBIT = %01000000 ; must be set to 1
DISP_FLIP = %00100000
DMA_ENABLE = %00010000 ; must be set to 1
PBKUP = $FD93 PBKUP = $FD93
DISPADRL = $FD94 DISPADRL = $FD94
DISPADRH = $FD95 DISPADRH = $FD95
MTEST0 = $FD9C MTEST0 = $FD9C
; MTEST0 bit definitions
AT_CNT16 = %10000000
AT_TEST = %01000000
XCLKEN = %00100000
UART_TURBO = %00010000
ROM_SEL = %00001000
ROM_TEST = %00000100
M_TEST = %00000010
CPU_TEST = %00000001
MTEST1 = $FD9D MTEST1 = $FD9D
; MTEST1 bit definitions
P_CNT16 = %01000000
REF_CNT16 = %00100000
VID_TRIG = %00010000
REF_TRIG = %00001000
VID_DMA_DIS = %00000100
REF_FAST = %00000010
REF_DIS = %00000001
MTEST2 = $FD9E MTEST2 = $FD9E
; MTEST2 bit definitions
V_STROBE = %00010000
V_ZERO = %00001000
H_120 = %00000100
H_ZERO = %00000010
V_BLANKEF = %00000001
PALETTE = $FDA0 ; hardware rgb palette PALETTE = $FDA0 ; hardware rgb palette
GCOLMAP = $FDA0 ; hardware rgb palette (green) GCOLMAP = $FDA0 ; hardware rgb palette (green)
RBCOLMAP = $FDB0 ; hardware rgb palette (red-blue) RBCOLMAP = $FDB0 ; hardware rgb palette (red-blue)
; Memory mapping control and 6502 vectors
; ***
; *** Misc Hardware + 6502 vectors
; ***
MAPCTL = $FFF9 MAPCTL = $FFF9
; MAPCTL bit definitions
TURBO_DISABLE = %10000000
VECTOR_SPACE = %00001000 ; 1 maps RAM into specified space
ROM_SPACE = %00000100
MIKEY_SPACE = %00000010
SUZY_SPACE = %00000001
VECTORS = $FFFB VECTORS = $FFFB
INTVECTL = $FFFE INTVECTL = $FFFE
INTVECTH = $FFFF INTVECTH = $FFFF
@@ -324,4 +424,3 @@ RSTVECTL = $FFFC
RSTVECTH = $FFFD RSTVECTH = $FFFD
NMIVECTL = $FFFA NMIVECTL = $FFFA
NMIVECTH = $FFFB NMIVECTH = $FFFB

165
include/_mikey.h
View File

@@ -27,7 +27,7 @@
#ifndef __MIKEY_H #ifndef __MIKEY_H
#define __MIKEY_H #define __MIKEY_H
/* timer structure */ /* Timer structure */
typedef struct _mikey_timer { typedef struct _mikey_timer {
unsigned char reload; unsigned char reload;
unsigned char control; unsigned char control;
@@ -39,7 +39,7 @@ typedef struct _mikey_all_timers {
struct _mikey_timer timer[8]; struct _mikey_timer timer[8];
} _mikey_all_timers; } _mikey_all_timers;
/* audio channel structure */ /* Audio channel structure */
typedef struct _mikey_audio { typedef struct _mikey_audio {
unsigned char volume; unsigned char volume;
unsigned char feedback; unsigned char feedback;
@@ -98,9 +98,168 @@ struct __mikey {
unsigned char mtest2; // 0xFD9E unsigned char mtest2; // 0xFD9E
unsigned char unused5; // 0xFD9F not used unsigned char unused5; // 0xFD9F not used
unsigned char palette[32]; // 0xFDA0 - 0xFDBF palette 32 bytes unsigned char palette[32]; // 0xFDA0 - 0xFDBF palette 32 bytes
// 0xFDC0 - 0xFDFF not used unsigned char unused6[64]; // 0xFDC0 - 0xFDFF not used
unsigned char bootrom[504]; // 0xFE00 - 0xFFD8 boot rom
unsigned char reserved; // 0xFFD8 reserved for future hardware
unsigned char mapctl; // 0xFFF9 map control register
struct {
unsigned char *nmi; // 0xFFFA NMI vector
unsigned char *reset; // 0xFFFB reset vector
unsigned char *irq; // 0xFFFC IRQ vector
} vectors;
}; };
// TIM_CONTROLA control bit definitions
enum {
ENABLE_INT = 0x80,
RESET_DONE = 0x40,
ENABLE_RELOAD = 0x10,
ENABLE_COUNT = 0x08
};
// AUD_CONTROL control bit definitions
enum {
FEEDBACK_7 = 0x80,
ENABLE_INTEGRATE = 0x20
};
// Audio and timer clock settings for source period
enum {
AUD_LINKING = 0x07,
AUD_64 = 0x06,
AUD_32 = 0x05,
AUD_16 = 0x04,
AUD_8 = 0x03,
AUD_4 = 0x02,
AUD_2 = 0x01,
AUD_1 = 0x00
};
// TIM_CONTROLB control bit definitions
enum {
TIMER_DONE = 0x08,
LAST_CLOCK = 0x04,
BORROW_IN = 0x02,
BORROW_OUT = 0x01
};
// MPAN and MSTEREO registers bit definitions
enum {
LEFT3_SELECT = 0x80,
LEFT2_SELECT = 0x40,
LEFT1_SELECT = 0x20,
LEFT0_SELECT = 0x10,
RIGHT3_SELECT = 0x08,
RIGHT2_SELECT = 0x04,
RIGHT1_SELECT = 0x02,
RIGHT0_SELECT = 0x01,
LEFT_ATTENMASK = 0xF0,
RIGHT_ATTENMASK = 0x0F
};
// Interrupt Reset and Set bit definitions
enum {
TIMER7_INT = 0x80,
TIMER6_INT = 0x40,
TIMER5_INT = 0x20,
TIMER4_INT = 0x10,
TIMER3_INT = 0x08,
TIMER2_INT = 0x04,
TIMER1_INT = 0x02,
TIMER0_INT = 0x01,
SERIAL_INT = TIMER4_INT,
VERTICAL_INT = TIMER2_INT,
HORIZONTAL_INT = TIMER0_INT
};
// SYSCTL1 bit definitions
enum {
POWERON = 0x02,
CART_ADDR_STROBE = 0x01
};
// IODIR and IODAT bit definitions
enum {
AUDIN_BIT = 0x10, // different from AUDIN address
READ_ENABLE = 0x10, // same bit for AUDIN_BIT
RESTLESS = 0x08,
NOEXP = 0x04, // if set, redeye is not connected
CART_ADDR_DATA = 0x02, //
CART_POWER_OFF = 0x02, // same bit for CART_ADDR_DATA
EXTERNAL_POWER = 0x01
};
// SERCTL bit definitions for write operations
enum {
TXINTEN = 0x80,
RXINTEN = 0x40,
PAREN = 0x10,
RESETERR = 0x08,
TXOPEN = 0x04,
TXBRK = 0x02,
PAREVEN = 0x01
};
// SERCTL bit definitions for read operations
enum {
TXRDY = 0x80,
RXRDY = 0x40,
TXEMPTY = 0x20,
PARERR = 0x10,
OVERRUN = 0x08,
FRAMERR = 0x04,
RXBRK = 0x02,
PARBIT = 0x01
};
// DISPCTL bit definitions
enum {
DISP_COLOR = 0x08, // must be set to 1
DISP_FOURBIT = 0x04, // must be set to 1
DISP_FLIP = 0x02, //
DMA_ENABLE = 0x01 // must be set to 1
};
// MTEST0 bit definitions
enum {
AT_CNT16 = 0x80,
AT_TEST = 0x40,
XCLKEN = 0x20,
UART_TURBO = 0x10,
ROM_SEL = 0x08,
ROM_TEST = 0x04,
M_TEST = 0x02,
CPU_TEST = 0x01
};
// MTEST1 bit definitions
enum {
P_CNT16 = 0x40,
REF_CNT16 = 0x20,
VID_TRIG = 0x10,
REF_TRIG = 0x08,
VID_DMA_DIS = 0x04,
REF_FAST = 0x02,
REF_DIS = 0x01
};
// MTEST2 bit definitions
enum {
V_STROBE = 0x10,
V_ZERO = 0x08,
H_120 = 0x04,
H_ZERO = 0x02,
V_BLANKEF = 0x01
};
// MAPCTL bit definitions
enum {
TURBO_DISABLE = 0x80,
VECTOR_SPACE = 0x08,
ROM_SPACE = 0x04,
MIKEY_SPACE = 0x02,
SUZY_SPACE = 0x01
};
#endif #endif