Rewrite RAM modules to use common slave implementation
This commit is contained in:
Alex Forencich
@@ -1,6 +1,6 @@
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"""
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Copyright (c) 2020 Alex Forencich
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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@@ -22,202 +22,32 @@ THE SOFTWARE.
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"""
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import logging
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import cocotb
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from .version import __version__
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from .constants import AxiProt, AxiResp
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from .axil_channels import AxiLiteAWSink, AxiLiteWSink, AxiLiteBSource, AxiLiteARSink, AxiLiteRSource
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from .axil_slave import AxiLiteSlaveWrite, AxiLiteSlaveRead
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from .memory import Memory
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from .reset import Reset
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class AxiLiteRamWrite(Memory, Reset):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
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self.bus = bus
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self.clock = clock
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self.reset = reset
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self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
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class AxiLiteRamWrite(AxiLiteSlaveWrite, Memory):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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self.log.info("AXI lite RAM model (write)")
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self.log.info("cocotbext-axi version %s", __version__)
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.log.info("https://github.com/alexforencich/cocotbext-axi")
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super().__init__(size, mem, *args, **kwargs)
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self.aw_channel = AxiLiteAWSink(bus.aw, clock, reset, reset_active_level)
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self.aw_channel.queue_occupancy_limit = 2
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self.w_channel = AxiLiteWSink(bus.w, clock, reset, reset_active_level)
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self.w_channel.queue_occupancy_limit = 2
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self.b_channel = AxiLiteBSource(bus.b, clock, reset, reset_active_level)
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self.b_channel.queue_occupancy_limit = 2
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self.address_width = len(self.aw_channel.bus.awaddr)
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self.width = len(self.w_channel.bus.wdata)
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self.byte_size = 8
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self.byte_lanes = self.width // self.byte_size
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self.strb_mask = 2**self.byte_lanes-1
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self.log.info("AXI lite RAM model configuration:")
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self.log.info(" Memory size: %d bytes", len(self.mem))
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self.log.info(" Address width: %d bits", self.address_width)
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
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self.log.info("AXI lite RAM model signals:")
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for bus in (self.bus.aw, self.bus.w, self.bus.b):
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for sig in sorted(list(set().union(bus._signals, bus._optional_signals))):
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if hasattr(bus, sig):
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self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig)))
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else:
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self.log.info(" %s: not present", sig)
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assert self.byte_lanes == len(self.w_channel.bus.wstrb)
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assert self.byte_lanes * self.byte_size == self.width
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self._process_write_cr = None
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self._init_reset(reset, reset_active_level)
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def _handle_reset(self, state):
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if state:
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self.log.info("Reset asserted")
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if self._process_write_cr is not None:
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self._process_write_cr.kill()
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self._process_write_cr = None
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self.aw_channel.clear()
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self.w_channel.clear()
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self.b_channel.clear()
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else:
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self.log.info("Reset de-asserted")
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if self._process_write_cr is None:
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self._process_write_cr = cocotb.fork(self._process_write())
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async def _process_write(self):
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while True:
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aw = await self.aw_channel.recv()
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addr = (int(aw.awaddr) // self.byte_lanes) * self.byte_lanes
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prot = AxiProt(getattr(aw, 'awprot', AxiProt.NONSECURE))
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w = await self.w_channel.recv()
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data = int(w.wdata)
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strb = int(getattr(w, 'wstrb', self.strb_mask))
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# todo latency
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self.mem.seek(addr % self.size)
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data = data.to_bytes(self.byte_lanes, 'little')
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if self.log.isEnabledFor(logging.INFO):
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self.log.info("Write data awaddr: 0x%08x awprot: %s wstrb: 0x%02x data: %s",
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addr, prot, strb, ' '.join((f'{c:02x}' for c in data)))
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for i in range(self.byte_lanes):
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if strb & (1 << i):
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self.mem.write(data[i:i+1])
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else:
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self.mem.seek(1, 1)
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b = self.b_channel._transaction_obj()
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b.bresp = AxiResp.OKAY
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await self.b_channel.send(b)
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async def _write(self, address, data):
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self.write(address, data)
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class AxiLiteRamRead(Memory, Reset):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
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self.bus = bus
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self.clock = clock
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self.reset = reset
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self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
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class AxiLiteRamRead(AxiLiteSlaveRead, Memory):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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self.log.info("AXI lite RAM model (read)")
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self.log.info("cocotbext-axi version %s", __version__)
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.log.info("https://github.com/alexforencich/cocotbext-axi")
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super().__init__(size, mem, *args, **kwargs)
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self.ar_channel = AxiLiteARSink(bus.ar, clock, reset, reset_active_level)
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self.ar_channel.queue_occupancy_limit = 2
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self.r_channel = AxiLiteRSource(bus.r, clock, reset, reset_active_level)
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self.r_channel.queue_occupancy_limit = 2
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self.address_width = len(self.ar_channel.bus.araddr)
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self.width = len(self.r_channel.bus.rdata)
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self.byte_size = 8
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self.byte_lanes = self.width // self.byte_size
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self.log.info("AXI lite RAM model configuration:")
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self.log.info(" Memory size: %d bytes", len(self.mem))
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self.log.info(" Address width: %d bits", self.address_width)
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
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self.log.info("AXI lite RAM model signals:")
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for bus in (self.bus.ar, self.bus.r):
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for sig in sorted(list(set().union(bus._signals, bus._optional_signals))):
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if hasattr(bus, sig):
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self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig)))
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else:
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self.log.info(" %s: not present", sig)
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assert self.byte_lanes * self.byte_size == self.width
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self._process_read_cr = None
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self._init_reset(reset, reset_active_level)
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def _handle_reset(self, state):
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if state:
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self.log.info("Reset asserted")
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if self._process_read_cr is not None:
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self._process_read_cr.kill()
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self._process_read_cr = None
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self.ar_channel.clear()
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self.r_channel.clear()
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else:
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self.log.info("Reset de-asserted")
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if self._process_read_cr is None:
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self._process_read_cr = cocotb.fork(self._process_read())
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async def _process_read(self):
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while True:
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ar = await self.ar_channel.recv()
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addr = (int(ar.araddr) // self.byte_lanes) * self.byte_lanes
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prot = AxiProt(getattr(ar, 'arprot', AxiProt.NONSECURE))
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# todo latency
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self.mem.seek(addr % self.size)
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data = self.mem.read(self.byte_lanes)
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r = self.r_channel._transaction_obj()
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r.rdata = int.from_bytes(data, 'little')
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r.rresp = AxiResp.OKAY
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await self.r_channel.send(r)
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if self.log.isEnabledFor(logging.INFO):
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self.log.info("Read data araddr: 0x%08x arprot: %s data: %s",
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addr, prot, ' '.join((f'{c:02x}' for c in data)))
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async def _read(self, address, length):
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return self.read(address, length)
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class AxiLiteRam(Memory):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
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self.write_if = None
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self.read_if = None
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super().__init__(size, mem, *args, **kwargs)
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super().__init__(size, mem, **kwargs)
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self.write_if = AxiLiteRamWrite(bus.write, clock, reset, reset_active_level, mem=self.mem)
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self.read_if = AxiLiteRamRead(bus.read, clock, reset, reset_active_level, mem=self.mem)
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