Rewrite RAM modules to use common slave implementation
This commit is contained in:
Alex Forencich
@@ -1,6 +1,6 @@
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"""
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"""
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Copyright (c) 2020 Alex Forencich
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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of this software and associated documentation files (the "Software"), to deal
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@@ -22,288 +22,32 @@ THE SOFTWARE.
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"""
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"""
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import logging
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from .axi_slave import AxiSlaveWrite, AxiSlaveRead
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import cocotb
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from .version import __version__
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from .constants import AxiBurstType, AxiProt, AxiResp
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from .axi_channels import AxiAWSink, AxiWSink, AxiBSource, AxiARSink, AxiRSource
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from .memory import Memory
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from .memory import Memory
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from .reset import Reset
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class AxiRamWrite(Memory, Reset):
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class AxiRamWrite(AxiSlaveWrite, Memory):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
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self.bus = bus
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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self.clock = clock
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self.reset = reset
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self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
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self.log.info("AXI RAM model (write)")
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async def _write(self, address, data):
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self.log.info("cocotbext-axi version %s", __version__)
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self.write(address, data)
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.log.info("https://github.com/alexforencich/cocotbext-axi")
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super().__init__(size, mem, *args, **kwargs)
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self.aw_channel = AxiAWSink(bus.aw, clock, reset, reset_active_level)
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class AxiRamRead(AxiSlaveRead, Memory):
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self.aw_channel.queue_occupancy_limit = 2
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
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self.w_channel = AxiWSink(bus.w, clock, reset, reset_active_level)
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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self.w_channel.queue_occupancy_limit = 2
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self.b_channel = AxiBSource(bus.b, clock, reset, reset_active_level)
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self.b_channel.queue_occupancy_limit = 2
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self.address_width = len(self.aw_channel.bus.awaddr)
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async def _read(self, address, length):
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self.id_width = len(self.aw_channel.bus.awid)
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return self.read(address, length)
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self.width = len(self.w_channel.bus.wdata)
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self.byte_size = 8
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self.byte_lanes = self.width // self.byte_size
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self.strb_mask = 2**self.byte_lanes-1
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self.max_burst_size = (self.byte_lanes-1).bit_length()
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self.log.info("AXI RAM model configuration:")
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self.log.info(" Memory size: %d bytes", len(self.mem))
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self.log.info(" Address width: %d bits", self.address_width)
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self.log.info(" ID width: %d bits", self.id_width)
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
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self.log.info("AXI RAM model signals:")
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for bus in (self.bus.aw, self.bus.w, self.bus.b):
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for sig in sorted(list(set().union(bus._signals, bus._optional_signals))):
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if hasattr(bus, sig):
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self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig)))
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else:
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self.log.info(" %s: not present", sig)
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assert self.byte_lanes == len(self.w_channel.bus.wstrb)
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assert self.byte_lanes * self.byte_size == self.width
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assert len(self.b_channel.bus.bid) == len(self.aw_channel.bus.awid)
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self._process_write_cr = None
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self._init_reset(reset, reset_active_level)
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def _handle_reset(self, state):
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if state:
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self.log.info("Reset asserted")
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if self._process_write_cr is not None:
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self._process_write_cr.kill()
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self._process_write_cr = None
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self.aw_channel.clear()
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self.w_channel.clear()
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self.b_channel.clear()
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else:
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self.log.info("Reset de-asserted")
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if self._process_write_cr is None:
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self._process_write_cr = cocotb.fork(self._process_write())
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async def _process_write(self):
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while True:
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aw = await self.aw_channel.recv()
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awid = int(getattr(aw, 'awid', 0))
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addr = int(aw.awaddr)
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length = int(getattr(aw, 'awlen', 0))
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size = int(getattr(aw, 'awsize', self.max_burst_size))
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burst = AxiBurstType(getattr(aw, 'awburst', AxiBurstType.INCR))
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prot = AxiProt(getattr(aw, 'awprot', AxiProt.NONSECURE))
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self.log.info("Write burst awid: 0x%x awaddr: 0x%08x awlen: %d awsize: %d awprot: %s",
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awid, addr, length, size, prot)
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num_bytes = 2**size
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assert 0 < num_bytes <= self.byte_lanes
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aligned_addr = (addr // num_bytes) * num_bytes
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length += 1
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transfer_size = num_bytes*length
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if burst == AxiBurstType.WRAP:
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lower_wrap_boundary = (addr // transfer_size) * transfer_size
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upper_wrap_boundary = lower_wrap_boundary + transfer_size
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if burst == AxiBurstType.INCR:
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# check 4k boundary crossing
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assert 0x1000-(aligned_addr & 0xfff) >= transfer_size
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cur_addr = aligned_addr
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for n in range(length):
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cur_word_addr = (cur_addr // self.byte_lanes) * self.byte_lanes
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w = await self.w_channel.recv()
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data = int(w.wdata)
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strb = int(getattr(w, 'wstrb', self.strb_mask))
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last = int(w.wlast)
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# todo latency
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self.mem.seek(cur_word_addr % self.size)
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data = data.to_bytes(self.byte_lanes, 'little')
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if self.log.isEnabledFor(logging.DEBUG):
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self.log.debug("Write word awid: 0x%x addr: 0x%08x wstrb: 0x%02x data: %s",
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awid, cur_addr, strb, ' '.join((f'{c:02x}' for c in data)))
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for i in range(self.byte_lanes):
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if strb & (1 << i):
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self.mem.write(data[i:i+1])
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else:
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self.mem.seek(1, 1)
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assert last == (n == length-1)
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if burst != AxiBurstType.FIXED:
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cur_addr += num_bytes
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if burst == AxiBurstType.WRAP:
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if cur_addr == upper_wrap_boundary:
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cur_addr = lower_wrap_boundary
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b = self.b_channel._transaction_obj()
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b.bid = awid
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b.bresp = AxiResp.OKAY
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await self.b_channel.send(b)
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class AxiRamRead(Memory, Reset):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
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self.bus = bus
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self.clock = clock
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self.reset = reset
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self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
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self.log.info("AXI RAM model (read)")
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self.log.info("cocotbext-axi version %s", __version__)
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.log.info("https://github.com/alexforencich/cocotbext-axi")
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super().__init__(size, mem, *args, **kwargs)
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self.ar_channel = AxiARSink(bus.ar, clock, reset, reset_active_level)
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self.ar_channel.queue_occupancy_limit = 2
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self.r_channel = AxiRSource(bus.r, clock, reset, reset_active_level)
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self.r_channel.queue_occupancy_limit = 2
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self.address_width = len(self.ar_channel.bus.araddr)
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self.id_width = len(self.ar_channel.bus.arid)
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self.width = len(self.r_channel.bus.rdata)
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self.byte_size = 8
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self.byte_lanes = self.width // self.byte_size
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self.max_burst_size = (self.byte_lanes-1).bit_length()
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self.log.info("AXI RAM model configuration:")
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self.log.info(" Memory size: %d bytes", len(self.mem))
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self.log.info(" Address width: %d bits", self.address_width)
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self.log.info(" ID width: %d bits", self.id_width)
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
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self.log.info("AXI RAM model signals:")
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for bus in (self.bus.ar, self.bus.r):
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for sig in sorted(list(set().union(bus._signals, bus._optional_signals))):
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if hasattr(bus, sig):
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self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig)))
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else:
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self.log.info(" %s: not present", sig)
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assert self.byte_lanes * self.byte_size == self.width
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assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid)
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self._process_read_cr = None
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self._init_reset(reset, reset_active_level)
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def _handle_reset(self, state):
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if state:
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self.log.info("Reset asserted")
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if self._process_read_cr is not None:
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self._process_read_cr.kill()
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self._process_read_cr = None
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self.ar_channel.clear()
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self.r_channel.clear()
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else:
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self.log.info("Reset de-asserted")
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if self._process_read_cr is None:
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self._process_read_cr = cocotb.fork(self._process_read())
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async def _process_read(self):
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while True:
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ar = await self.ar_channel.recv()
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arid = int(getattr(ar, 'arid', 0))
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addr = int(ar.araddr)
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length = int(getattr(ar, 'arlen', 0))
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size = int(getattr(ar, 'arsize', self.max_burst_size))
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burst = AxiBurstType(getattr(ar, 'arburst', AxiBurstType.INCR))
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prot = AxiProt(getattr(ar, 'arprot', AxiProt.NONSECURE))
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self.log.info("Read burst arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d arprot: %s",
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arid, addr, length, size, prot)
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num_bytes = 2**size
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assert 0 < num_bytes <= self.byte_lanes
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aligned_addr = (addr // num_bytes) * num_bytes
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length += 1
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transfer_size = num_bytes*length
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if burst == AxiBurstType.WRAP:
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lower_wrap_boundary = (addr // transfer_size) * transfer_size
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upper_wrap_boundary = lower_wrap_boundary + transfer_size
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if burst == AxiBurstType.INCR:
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# check 4k boundary crossing
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assert 0x1000-(aligned_addr & 0xfff) >= transfer_size
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cur_addr = aligned_addr
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for n in range(length):
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cur_word_addr = (cur_addr // self.byte_lanes) * self.byte_lanes
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self.mem.seek(cur_word_addr % self.size)
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data = self.mem.read(self.byte_lanes)
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r = self.r_channel._transaction_obj()
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r.rid = arid
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r.rdata = int.from_bytes(data, 'little')
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r.rlast = n == length-1
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r.rresp = AxiResp.OKAY
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await self.r_channel.send(r)
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if self.log.isEnabledFor(logging.DEBUG):
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self.log.debug("Read word awid: 0x%x addr: 0x%08x data: %s",
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arid, cur_addr, ' '.join((f'{c:02x}' for c in data)))
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if burst != AxiBurstType.FIXED:
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cur_addr += num_bytes
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if burst == AxiBurstType.WRAP:
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if cur_addr == upper_wrap_boundary:
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cur_addr = lower_wrap_boundary
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class AxiRam(Memory):
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class AxiRam(Memory):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
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self.write_if = None
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self.write_if = None
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self.read_if = None
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self.read_if = None
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super().__init__(size, mem, *args, **kwargs)
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super().__init__(size, mem, **kwargs)
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self.write_if = AxiRamWrite(bus.write, clock, reset, reset_active_level, mem=self.mem)
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self.write_if = AxiRamWrite(bus.write, clock, reset, reset_active_level, mem=self.mem)
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self.read_if = AxiRamRead(bus.read, clock, reset, reset_active_level, mem=self.mem)
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self.read_if = AxiRamRead(bus.read, clock, reset, reset_active_level, mem=self.mem)
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@@ -1,6 +1,6 @@
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"""
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"""
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Copyright (c) 2020 Alex Forencich
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
of this software and associated documentation files (the "Software"), to deal
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
@@ -22,202 +22,32 @@ THE SOFTWARE.
|
|||||||
|
|
||||||
"""
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"""
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import logging
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from .axil_slave import AxiLiteSlaveWrite, AxiLiteSlaveRead
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import cocotb
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from .version import __version__
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from .constants import AxiProt, AxiResp
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from .axil_channels import AxiLiteAWSink, AxiLiteWSink, AxiLiteBSource, AxiLiteARSink, AxiLiteRSource
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from .memory import Memory
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from .memory import Memory
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from .reset import Reset
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class AxiLiteRamWrite(Memory, Reset):
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class AxiLiteRamWrite(AxiLiteSlaveWrite, Memory):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
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self.bus = bus
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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self.clock = clock
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self.reset = reset
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self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
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self.log.info("AXI lite RAM model (write)")
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async def _write(self, address, data):
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self.log.info("cocotbext-axi version %s", __version__)
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self.write(address, data)
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.log.info("https://github.com/alexforencich/cocotbext-axi")
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|
||||||
super().__init__(size, mem, *args, **kwargs)
|
|
||||||
|
|
||||||
self.aw_channel = AxiLiteAWSink(bus.aw, clock, reset, reset_active_level)
|
|
||||||
self.aw_channel.queue_occupancy_limit = 2
|
|
||||||
self.w_channel = AxiLiteWSink(bus.w, clock, reset, reset_active_level)
|
|
||||||
self.w_channel.queue_occupancy_limit = 2
|
|
||||||
self.b_channel = AxiLiteBSource(bus.b, clock, reset, reset_active_level)
|
|
||||||
self.b_channel.queue_occupancy_limit = 2
|
|
||||||
|
|
||||||
self.address_width = len(self.aw_channel.bus.awaddr)
|
|
||||||
self.width = len(self.w_channel.bus.wdata)
|
|
||||||
self.byte_size = 8
|
|
||||||
self.byte_lanes = self.width // self.byte_size
|
|
||||||
self.strb_mask = 2**self.byte_lanes-1
|
|
||||||
|
|
||||||
self.log.info("AXI lite RAM model configuration:")
|
|
||||||
self.log.info(" Memory size: %d bytes", len(self.mem))
|
|
||||||
self.log.info(" Address width: %d bits", self.address_width)
|
|
||||||
self.log.info(" Byte size: %d bits", self.byte_size)
|
|
||||||
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
|
|
||||||
|
|
||||||
self.log.info("AXI lite RAM model signals:")
|
|
||||||
for bus in (self.bus.aw, self.bus.w, self.bus.b):
|
|
||||||
for sig in sorted(list(set().union(bus._signals, bus._optional_signals))):
|
|
||||||
if hasattr(bus, sig):
|
|
||||||
self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig)))
|
|
||||||
else:
|
|
||||||
self.log.info(" %s: not present", sig)
|
|
||||||
|
|
||||||
assert self.byte_lanes == len(self.w_channel.bus.wstrb)
|
|
||||||
assert self.byte_lanes * self.byte_size == self.width
|
|
||||||
|
|
||||||
self._process_write_cr = None
|
|
||||||
|
|
||||||
self._init_reset(reset, reset_active_level)
|
|
||||||
|
|
||||||
def _handle_reset(self, state):
|
|
||||||
if state:
|
|
||||||
self.log.info("Reset asserted")
|
|
||||||
if self._process_write_cr is not None:
|
|
||||||
self._process_write_cr.kill()
|
|
||||||
self._process_write_cr = None
|
|
||||||
|
|
||||||
self.aw_channel.clear()
|
|
||||||
self.w_channel.clear()
|
|
||||||
self.b_channel.clear()
|
|
||||||
else:
|
|
||||||
self.log.info("Reset de-asserted")
|
|
||||||
if self._process_write_cr is None:
|
|
||||||
self._process_write_cr = cocotb.fork(self._process_write())
|
|
||||||
|
|
||||||
async def _process_write(self):
|
|
||||||
while True:
|
|
||||||
aw = await self.aw_channel.recv()
|
|
||||||
|
|
||||||
addr = (int(aw.awaddr) // self.byte_lanes) * self.byte_lanes
|
|
||||||
prot = AxiProt(getattr(aw, 'awprot', AxiProt.NONSECURE))
|
|
||||||
|
|
||||||
w = await self.w_channel.recv()
|
|
||||||
|
|
||||||
data = int(w.wdata)
|
|
||||||
strb = int(getattr(w, 'wstrb', self.strb_mask))
|
|
||||||
|
|
||||||
# todo latency
|
|
||||||
|
|
||||||
self.mem.seek(addr % self.size)
|
|
||||||
|
|
||||||
data = data.to_bytes(self.byte_lanes, 'little')
|
|
||||||
|
|
||||||
if self.log.isEnabledFor(logging.INFO):
|
|
||||||
self.log.info("Write data awaddr: 0x%08x awprot: %s wstrb: 0x%02x data: %s",
|
|
||||||
addr, prot, strb, ' '.join((f'{c:02x}' for c in data)))
|
|
||||||
|
|
||||||
for i in range(self.byte_lanes):
|
|
||||||
if strb & (1 << i):
|
|
||||||
self.mem.write(data[i:i+1])
|
|
||||||
else:
|
|
||||||
self.mem.seek(1, 1)
|
|
||||||
|
|
||||||
b = self.b_channel._transaction_obj()
|
|
||||||
b.bresp = AxiResp.OKAY
|
|
||||||
|
|
||||||
await self.b_channel.send(b)
|
|
||||||
|
|
||||||
|
|
||||||
class AxiLiteRamRead(Memory, Reset):
|
class AxiLiteRamRead(AxiLiteSlaveRead, Memory):
|
||||||
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
|
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
|
||||||
self.bus = bus
|
super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
|
||||||
self.clock = clock
|
|
||||||
self.reset = reset
|
|
||||||
self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
|
|
||||||
|
|
||||||
self.log.info("AXI lite RAM model (read)")
|
async def _read(self, address, length):
|
||||||
self.log.info("cocotbext-axi version %s", __version__)
|
return self.read(address, length)
|
||||||
self.log.info("Copyright (c) 2020 Alex Forencich")
|
|
||||||
self.log.info("https://github.com/alexforencich/cocotbext-axi")
|
|
||||||
|
|
||||||
super().__init__(size, mem, *args, **kwargs)
|
|
||||||
|
|
||||||
self.ar_channel = AxiLiteARSink(bus.ar, clock, reset, reset_active_level)
|
|
||||||
self.ar_channel.queue_occupancy_limit = 2
|
|
||||||
self.r_channel = AxiLiteRSource(bus.r, clock, reset, reset_active_level)
|
|
||||||
self.r_channel.queue_occupancy_limit = 2
|
|
||||||
|
|
||||||
self.address_width = len(self.ar_channel.bus.araddr)
|
|
||||||
self.width = len(self.r_channel.bus.rdata)
|
|
||||||
self.byte_size = 8
|
|
||||||
self.byte_lanes = self.width // self.byte_size
|
|
||||||
|
|
||||||
self.log.info("AXI lite RAM model configuration:")
|
|
||||||
self.log.info(" Memory size: %d bytes", len(self.mem))
|
|
||||||
self.log.info(" Address width: %d bits", self.address_width)
|
|
||||||
self.log.info(" Byte size: %d bits", self.byte_size)
|
|
||||||
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
|
|
||||||
|
|
||||||
self.log.info("AXI lite RAM model signals:")
|
|
||||||
for bus in (self.bus.ar, self.bus.r):
|
|
||||||
for sig in sorted(list(set().union(bus._signals, bus._optional_signals))):
|
|
||||||
if hasattr(bus, sig):
|
|
||||||
self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig)))
|
|
||||||
else:
|
|
||||||
self.log.info(" %s: not present", sig)
|
|
||||||
|
|
||||||
assert self.byte_lanes * self.byte_size == self.width
|
|
||||||
|
|
||||||
self._process_read_cr = None
|
|
||||||
|
|
||||||
self._init_reset(reset, reset_active_level)
|
|
||||||
|
|
||||||
def _handle_reset(self, state):
|
|
||||||
if state:
|
|
||||||
self.log.info("Reset asserted")
|
|
||||||
if self._process_read_cr is not None:
|
|
||||||
self._process_read_cr.kill()
|
|
||||||
self._process_read_cr = None
|
|
||||||
|
|
||||||
self.ar_channel.clear()
|
|
||||||
self.r_channel.clear()
|
|
||||||
else:
|
|
||||||
self.log.info("Reset de-asserted")
|
|
||||||
if self._process_read_cr is None:
|
|
||||||
self._process_read_cr = cocotb.fork(self._process_read())
|
|
||||||
|
|
||||||
async def _process_read(self):
|
|
||||||
while True:
|
|
||||||
ar = await self.ar_channel.recv()
|
|
||||||
|
|
||||||
addr = (int(ar.araddr) // self.byte_lanes) * self.byte_lanes
|
|
||||||
prot = AxiProt(getattr(ar, 'arprot', AxiProt.NONSECURE))
|
|
||||||
|
|
||||||
# todo latency
|
|
||||||
|
|
||||||
self.mem.seek(addr % self.size)
|
|
||||||
|
|
||||||
data = self.mem.read(self.byte_lanes)
|
|
||||||
|
|
||||||
r = self.r_channel._transaction_obj()
|
|
||||||
r.rdata = int.from_bytes(data, 'little')
|
|
||||||
r.rresp = AxiResp.OKAY
|
|
||||||
|
|
||||||
await self.r_channel.send(r)
|
|
||||||
|
|
||||||
if self.log.isEnabledFor(logging.INFO):
|
|
||||||
self.log.info("Read data araddr: 0x%08x arprot: %s data: %s",
|
|
||||||
addr, prot, ' '.join((f'{c:02x}' for c in data)))
|
|
||||||
|
|
||||||
|
|
||||||
class AxiLiteRam(Memory):
|
class AxiLiteRam(Memory):
|
||||||
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
|
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
|
||||||
self.write_if = None
|
self.write_if = None
|
||||||
self.read_if = None
|
self.read_if = None
|
||||||
|
|
||||||
super().__init__(size, mem, *args, **kwargs)
|
super().__init__(size, mem, **kwargs)
|
||||||
|
|
||||||
self.write_if = AxiLiteRamWrite(bus.write, clock, reset, reset_active_level, mem=self.mem)
|
self.write_if = AxiLiteRamWrite(bus.write, clock, reset, reset_active_level, mem=self.mem)
|
||||||
self.read_if = AxiLiteRamRead(bus.read, clock, reset, reset_active_level, mem=self.mem)
|
self.read_if = AxiLiteRamRead(bus.read, clock, reset, reset_active_level, mem=self.mem)
|
||||||
|
|||||||
Reference in New Issue
Block a user