From 28bc97f22679d5752e7b71ed2317ad058c677f17 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Fri, 26 May 2023 16:33:34 -0700
Subject: [PATCH] Remove recursively-expanded macros for module parameters in
 makefiles

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 tests/axi/Makefile  | 18 +++++++++---------
 tests/axil/Makefile |  6 +++---
 tests/axis/Makefile | 10 +++++-----
 3 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/tests/axi/Makefile b/tests/axi/Makefile
index 07272d0..932e8b9 100644
--- a/tests/axi/Makefile
+++ b/tests/axi/Makefile
@@ -32,15 +32,15 @@ MODULE   = $(DUT)
 VERILOG_SOURCES += $(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 32
-export PARAM_ADDR_WIDTH ?= 32
-export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
-export PARAM_ID_WIDTH ?= 8
-export PARAM_AWUSER_WIDTH ?= 1
-export PARAM_WUSER_WIDTH ?= 1
-export PARAM_BUSER_WIDTH ?= 1
-export PARAM_ARUSER_WIDTH ?= 1
-export PARAM_RUSER_WIDTH ?= 1
+export PARAM_DATA_WIDTH := 32
+export PARAM_ADDR_WIDTH := 32
+export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_ID_WIDTH := 8
+export PARAM_AWUSER_WIDTH := 1
+export PARAM_WUSER_WIDTH := 1
+export PARAM_BUSER_WIDTH := 1
+export PARAM_ARUSER_WIDTH := 1
+export PARAM_RUSER_WIDTH := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tests/axil/Makefile b/tests/axil/Makefile
index dac130c..da366a4 100644
--- a/tests/axil/Makefile
+++ b/tests/axil/Makefile
@@ -32,9 +32,9 @@ MODULE   = $(DUT)
 VERILOG_SOURCES += $(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 32
-export PARAM_ADDR_WIDTH ?= 32
-export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_DATA_WIDTH := 32
+export PARAM_ADDR_WIDTH := 32
+export PARAM_STRB_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
diff --git a/tests/axis/Makefile b/tests/axis/Makefile
index 7b4a37b..4724e0c 100644
--- a/tests/axis/Makefile
+++ b/tests/axis/Makefile
@@ -32,11 +32,11 @@ MODULE   = $(DUT)
 VERILOG_SOURCES += $(DUT).v
 
 # module parameters
-export PARAM_DATA_WIDTH ?= 8
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
-export PARAM_ID_WIDTH ?= 8
-export PARAM_DEST_WIDTH ?= 8
-export PARAM_USER_WIDTH ?= 1
+export PARAM_DATA_WIDTH := 8
+export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_ID_WIDTH := 8
+export PARAM_DEST_WIDTH := 8
+export PARAM_USER_WIDTH := 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst