Remove extraneous code

This commit is contained in:
Alex Forencich
2022-01-04 15:28:48 -08:00
parent 0f20e2e9bf
commit 35d9742ae8

View File

@@ -63,7 +63,6 @@ class AxiLiteSlaveWrite(Reset):
self.wstrb_present = hasattr(self.bus.w, "wstrb") self.wstrb_present = hasattr(self.bus.w, "wstrb")
self.log.info("AXI lite slave model configuration:") self.log.info("AXI lite slave model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", self.address_width) self.log.info(" Address width: %d bits", self.address_width)
self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
@@ -182,7 +181,6 @@ class AxiLiteSlaveRead(Reset):
self.byte_lanes = self.width // self.byte_size self.byte_lanes = self.width // self.byte_size
self.log.info("AXI lite slave model configuration:") self.log.info("AXI lite slave model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", self.address_width) self.log.info(" Address width: %d bits", self.address_width)
self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)