Initial commit
This commit is contained in:
Alex Forencich
470
cocotbext/axi/axi_ram.py
Normal file
470
cocotbext/axi/axi_ram.py
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"""
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import cocotb
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from cocotb.triggers import RisingEdge, ReadOnly, Event
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from cocotb.drivers import BusDriver
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import mmap
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from collections import deque
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from .constants import *
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class AxiRamWrite(BusDriver):
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_signals = [
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# Write address channel
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"awid", "awaddr", "awlen", "awsize", "awburst", "awprot", "awvalid", "awready",
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# Write data channel
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"wdata", "wstrb", "wlast", "wvalid", "wready",
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# Write response channel
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"bid", "bresp", "bvalid", "bready",
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]
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_optional_signals = [
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# Write address channel
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"awlock", "awcache", "awqos", "awregion", "awuser",
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# Write data channel
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"wuser",
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# Write response channel
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"buser",
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]
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def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
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super().__init__(entity, name, clock)
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if type(mem) is mmap.mmap:
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self.mem = mem
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else:
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self.mem = mmap.mmap(-1, size)
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self.size = len(self.mem)
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self.int_write_addr_queue = deque()
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self.int_write_addr_sync = Event()
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self.int_write_data_queue = deque()
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self.int_write_data_sync = Event()
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self.int_write_resp_queue = deque()
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self.int_write_resp_sync = Event()
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self.in_flight_operations = 0
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self.width = len(self.bus.wdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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self.strb_mask = 2**len(self.bus.wstrb)-1
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assert self.byte_width == len(self.bus.wstrb)
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assert self.byte_width * self.byte_size == self.width
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self.reset = reset
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assert len(self.bus.awlen) == 8
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assert len(self.bus.awsize) == 3
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assert len(self.bus.awburst) == 2
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if hasattr(self.bus, "awlock"):
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assert len(self.bus.awlock) == 1
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if hasattr(self.bus, "awcache"):
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assert len(self.bus.awcache) == 4
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assert len(self.bus.awprot) == 3
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if hasattr(self.bus, "awqos"):
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assert len(self.bus.awqos) == 4
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if hasattr(self.bus, "awregion"):
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assert len(self.bus.awregion) == 4
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assert len(self.bus.awvalid) == 1
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assert len(self.bus.awready) == 1
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self.bus.awready.setimmediatevalue(0)
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assert len(self.bus.wlast) == 1
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assert len(self.bus.wvalid) == 1
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assert len(self.bus.wready) == 1
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self.bus.wready.setimmediatevalue(0)
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assert len(self.bus.bid) == len(self.bus.awid)
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self.bus.bid.setimmediatevalue(0)
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assert len(self.bus.bresp) == 2
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self.bus.bresp.setimmediatevalue(0)
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assert len(self.bus.bvalid) == 1
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if hasattr(self.bus, "buser"):
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self.bus.buser.setimmediatevalue(0)
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self.bus.bvalid.setimmediatevalue(0)
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assert len(self.bus.bready) == 1
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cocotb.fork(self._process_write())
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cocotb.fork(self._process_write_addr_if())
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cocotb.fork(self._process_write_data_if())
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cocotb.fork(self._process_write_resp_if())
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def read_mem(self, address, length):
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self.mem.seek(address)
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return self.mem.read(length)
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def write_mem(self, address, data):
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self.mem.seek(address)
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self.mem.write(bytes(data))
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async def _process_write(self):
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while True:
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if not self.int_write_addr_queue:
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self.int_write_addr_sync.clear()
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await self.int_write_addr_sync.wait()
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awid, addr, length, size, burst, prot = self.int_write_addr_queue.popleft()
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prot = AxiProt(prot)
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self.log.info(f"Write burst awid: {awid:#x} awaddr: {addr:#010x} awlen: {length} awsize: {size} awprot: {prot}")
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num_bytes = 2**size
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assert 0 < num_bytes <= self.byte_width
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aligned_addr = (addr // num_bytes) * num_bytes
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length += 1
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transfer_size = num_bytes*length
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if burst == AxiBurstType.WRAP:
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lower_wrap_boundary = (addr // transfer_size) * transfer_size
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upper_wrap_boundary = lower_wrap_boundary + transfer_size
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if burst == AxiBurstType.INCR:
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# check 4k boundary crossing
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assert 0x1000-(aligned_addr&0xfff) >= transfer_size
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cur_addr = aligned_addr
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for n in range(length):
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cur_word_addr = (cur_addr // self.byte_width) * self.byte_width
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if not self.int_write_data_queue:
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self.int_write_data_sync.clear()
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await self.int_write_data_sync.wait()
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data, strb, last = self.int_write_data_queue.popleft()
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# todo latency
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self.mem.seek(cur_word_addr % self.size)
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data = data.to_bytes(self.byte_width, 'little')
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self.log.info(f"Write word awid: {awid:#x} addr: {cur_addr:#010x} wstrb: {strb:#04x} data: {' '.join((f'{c:02x}' for c in data))}")
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for i in range(self.byte_width):
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if strb & (1 << i):
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self.mem.write(data[i:i+1])
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else:
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self.mem.seek(1, 1)
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assert last == (n == length-1)
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if burst != AxiBurstType.FIXED:
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cur_addr += num_bytes
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if burst == AxiBurstType.WRAP:
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if cur_addr == upper_wrap_boundary:
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cur_addr = lower_wrap_boundary
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self.int_write_resp_queue.append((awid, AxiResp.OKAY))
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self.int_write_resp_sync.set()
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async def _process_write_addr_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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awready_sample = self.bus.awready.value
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awvalid_sample = self.bus.awvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.awready <= 0
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continue
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if awready_sample and awvalid_sample:
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awid = self.bus.awid.value.integer
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awaddr = self.bus.awaddr.value.integer
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awlen = self.bus.awlen.value.integer
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awsize = self.bus.awsize.value.integer
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awburst = self.bus.awburst.value.integer
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awprot = self.bus.awprot.value.integer
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self.int_write_addr_queue.append((awid, awaddr, awlen, awsize, awburst, awprot))
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self.int_write_addr_sync.set()
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await RisingEdge(self.clock)
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self.bus.awready <= 1
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async def _process_write_data_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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wready_sample = self.bus.wready.value
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wvalid_sample = self.bus.wvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.wready <= 0
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continue
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if wready_sample and wvalid_sample:
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wdata = self.bus.wdata.value.integer
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wstrb = self.bus.wstrb.value.integer
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wlast = self.bus.wlast.value.integer
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self.int_write_data_queue.append((wdata, wstrb, wlast))
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self.int_write_data_sync.set()
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await RisingEdge(self.clock)
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self.bus.wready <= 1
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async def _process_write_resp_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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bready_sample = self.bus.bready.value
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bvalid_sample = self.bus.bvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.bvalid <= 0
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continue
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await RisingEdge(self.clock)
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if (bready_sample and bvalid_sample) or (not bvalid_sample):
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if self.int_write_resp_queue:
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bid, bresp = self.int_write_resp_queue.popleft()
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self.bus.bid <= bid
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self.bus.bresp <= bresp
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self.bus.bvalid <= 1
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else:
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self.bus.bvalid <= 0
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class AxiRamRead(BusDriver):
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_signals = [
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# Read address channel
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"arid", "araddr", "arlen", "arsize", "arburst", "arprot", "arvalid", "arready",
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# Read data channel
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"rid", "rdata", "rresp", "rlast", "rvalid", "rready",
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]
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_optional_signals = [
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# Read address channel
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"arlock", "arcache", "arqos", "arregion", "aruser",
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# Read data channel
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"ruser",
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]
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def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
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super().__init__(entity, name, clock)
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if type(mem) is mmap.mmap:
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self.mem = mem
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else:
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self.mem = mmap.mmap(-1, size)
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self.size = len(self.mem)
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self.int_read_addr_queue = deque()
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self.int_read_addr_sync = Event()
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self.int_read_resp_command_queue = deque()
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self.int_read_resp_command_sync = Event()
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self.int_read_resp_queue = deque()
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self.int_read_resp_sync = Event()
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self.in_flight_operations = 0
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self.width = len(self.bus.rdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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assert self.byte_width * self.byte_size == self.width
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self.reset = reset
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assert len(self.bus.arlen) == 8
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assert len(self.bus.arsize) == 3
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assert len(self.bus.arburst) == 2
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if hasattr(self.bus, "arlock"):
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assert len(self.bus.arlock) == 1
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if hasattr(self.bus, "arcache"):
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assert len(self.bus.arcache) == 4
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assert len(self.bus.arprot) == 3
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if hasattr(self.bus, "arqos"):
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assert len(self.bus.arqos) == 4
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if hasattr(self.bus, "arregion"):
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assert len(self.bus.arregion) == 4
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assert len(self.bus.arvalid) == 1
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assert len(self.bus.arready) == 1
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self.bus.arready.setimmediatevalue(0)
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assert len(self.bus.rid) == len(self.bus.arid)
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self.bus.rid.setimmediatevalue(0)
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self.bus.rdata.setimmediatevalue(0)
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assert len(self.bus.rresp) == 2
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self.bus.rresp.setimmediatevalue(0)
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assert len(self.bus.rlast) == 1
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self.bus.rlast.setimmediatevalue(0)
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if hasattr(self.bus, "ruser"):
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self.bus.ruser.setimmediatevalue(0)
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assert len(self.bus.rvalid) == 1
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self.bus.rvalid.setimmediatevalue(0)
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assert len(self.bus.rready) == 1
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cocotb.fork(self._process_read())
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cocotb.fork(self._process_read_addr_if())
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cocotb.fork(self._process_read_resp_if())
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def read_mem(self, address, length):
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self.mem.seek(address)
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return self.mem.read(length)
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def write_mem(self, address, data):
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self.mem.seek(address)
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self.mem.write(bytes(data))
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async def _process_read(self):
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while True:
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if not self.int_read_addr_queue:
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self.int_read_addr_sync.clear()
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await self.int_read_addr_sync.wait()
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arid, addr, length, size, burst, prot = self.int_read_addr_queue.popleft()
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prot = AxiProt(prot)
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self.log.info(f"Read burst arid: {arid:#x} araddr: {addr:#010x} arlen: {length} arsize: {size} arprot: {prot}")
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num_bytes = 2**size
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assert 0 < num_bytes <= self.byte_width
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aligned_addr = (addr // num_bytes) * num_bytes
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length += 1
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transfer_size = num_bytes*length
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if burst == AxiBurstType.WRAP:
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lower_wrap_boundary = (addr // transfer_size) * transfer_size
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upper_wrap_boundary = lower_wrap_boundary + transfer_size
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if burst == AxiBurstType.INCR:
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# check 4k boundary crossing
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assert 0x1000-(aligned_addr&0xfff) >= transfer_size
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cur_addr = aligned_addr
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for n in range(length):
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cur_word_addr = (cur_addr // self.byte_width) * self.byte_width
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self.mem.seek(cur_word_addr % self.size)
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data = self.mem.read(self.byte_width)
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self.int_read_resp_queue.append((arid, int.from_bytes(data, 'little'), AxiResp.OKAY, n == length-1))
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self.int_read_resp_sync.set()
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self.log.info(f"Read word arid: {arid:#x} addr: {cur_addr:#010x} data: {' '.join((f'{c:02x}' for c in data))}")
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if burst != AxiBurstType.FIXED:
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cur_addr += num_bytes
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if burst == AxiBurstType.WRAP:
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if cur_addr == upper_wrap_boundary:
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cur_addr = lower_wrap_boundary
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async def _process_read_addr_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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arready_sample = self.bus.arready.value
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arvalid_sample = self.bus.arvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.arready <= 0
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continue
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if arready_sample and arvalid_sample:
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arid = self.bus.arid.value.integer
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araddr = self.bus.araddr.value.integer
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arlen = self.bus.arlen.value.integer
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arsize = self.bus.arsize.value.integer
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arburst = self.bus.arburst.value.integer
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arprot = self.bus.arprot.value.integer
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self.int_read_addr_queue.append((arid, araddr, arlen, arsize, arburst, arprot))
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self.int_read_addr_sync.set()
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await RisingEdge(self.clock)
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self.bus.arready <= 1
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async def _process_read_resp_if(self):
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while True:
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await ReadOnly()
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# read handshake signals
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rready_sample = self.bus.rready.value
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rvalid_sample = self.bus.rvalid.value
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if self.reset is not None and self.reset.value:
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await RisingEdge(self.clock)
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self.bus.rvalid <= 0
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continue
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await RisingEdge(self.clock)
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if (rready_sample and rvalid_sample) or (not rvalid_sample):
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if self.int_read_resp_queue:
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rid, rdata, rresp, rlast = self.int_read_resp_queue.popleft()
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self.bus.rid <= rid
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self.bus.rdata <= rdata
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self.bus.rresp <= rresp
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self.bus.rlast <= rlast
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self.bus.rvalid <= 1
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else:
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self.bus.rvalid <= 0
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class AxiRam(object):
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def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
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self.write_if = None
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self.read_if = None
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if type(mem) is mmap.mmap:
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self.mem = mem
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else:
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self.mem = mmap.mmap(-1, size)
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self.size = len(self.mem)
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self.write_if = AxiRamWrite(entity, name, clock, reset, mem=self.mem)
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self.read_if = AxiRamRead(entity, name, clock, reset, mem=self.mem)
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|
||||
def read_mem(self, address, length):
|
||||
self.mem.seek(address)
|
||||
return self.mem.read(length)
|
||||
|
||||
def write_mem(self, address, data):
|
||||
self.mem.seek(address)
|
||||
self.mem.write(bytes(data))
|
||||
|
||||
Reference in New Issue
Block a user