diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py
index 65282e1..ac42344 100644
--- a/cocotbext/axi/axi_master.py
+++ b/cocotbext/axi/axi_master.py
@@ -397,8 +397,9 @@ class AxiMasterWrite(Reset):
 
             wuser = cmd.wuser
 
-            self.log.info("Write start addr: 0x%08x awid: 0x%x prot: %s data: %s",
-                cmd.address, awid, cmd.prot, ' '.join((f'{c:02x}' for c in cmd.data)))
+            if self.log.isEnabledFor(logging.INFO):
+                self.log.info("Write start addr: 0x%08x awid: 0x%x prot: %s data: %s",
+                        cmd.address, awid, cmd.prot, ' '.join((f'{c:02x}' for c in cmd.data)))
 
             for k in range(cycles):
                 start = cycle_offset
@@ -444,7 +445,7 @@ class AxiMasterWrite(Reset):
                     await self.aw_channel.send(aw)
 
                     self.log.info("Write burst start awid: 0x%x awaddr: 0x%08x awlen: %d awsize: %d awprot: %s",
-                        awid, cur_addr, burst_length-1, cmd.size, cmd.prot)
+                            awid, cur_addr, burst_length-1, cmd.size, cmd.prot)
 
                 n += 1
 
@@ -511,7 +512,7 @@ class AxiMasterWrite(Reset):
             user = None
 
         self.log.info("Write complete addr: 0x%08x prot: %s resp: %s length: %d",
-            cmd.address, cmd.prot, resp, cmd.length)
+                cmd.address, cmd.prot, resp, cmd.length)
 
         write_resp = AxiWriteResp(cmd.address, cmd.length, resp, user)
 
@@ -795,7 +796,7 @@ class AxiMasterRead(Reset):
                     await self.ar_channel.send(ar)
 
                     self.log.info("Read burst start arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d arprot: %s",
-                        arid, cur_addr, burst_length-1, cmd.size, cmd.prot)
+                            arid, cur_addr, burst_length-1, cmd.size, cmd.prot)
 
                 cur_addr += num_bytes
 
@@ -884,8 +885,9 @@ class AxiMasterRead(Reset):
         if not self.ruser_present:
             user = None
 
-        self.log.info("Read complete addr: 0x%08x prot: %s resp: %s data: %s",
-            cmd.address, cmd.prot, resp, ' '.join((f'{c:02x}' for c in data)))
+        if self.log.isEnabledFor(logging.INFO):
+            self.log.info("Read complete addr: 0x%08x prot: %s resp: %s data: %s",
+                    cmd.address, cmd.prot, resp, ' '.join((f'{c:02x}' for c in data)))
 
         read_resp = AxiReadResp(cmd.address, data, resp, user)
 
diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py
index 487c399..5f5a500 100644
--- a/cocotbext/axi/axi_ram.py
+++ b/cocotbext/axi/axi_ram.py
@@ -112,7 +112,7 @@ class AxiRamWrite(Memory, Reset):
             prot = AxiProt(getattr(aw, 'awprot', AxiProt.NONSECURE))
 
             self.log.info("Write burst awid: 0x%x awaddr: 0x%08x awlen: %d awsize: %d awprot: %s",
-                awid, addr, length, size, prot)
+                    awid, addr, length, size, prot)
 
             num_bytes = 2**size
             assert 0 < num_bytes <= self.byte_lanes
@@ -147,8 +147,9 @@ class AxiRamWrite(Memory, Reset):
 
                 data = data.to_bytes(self.byte_lanes, 'little')
 
-                self.log.debug("Write word awid: 0x%x addr: 0x%08x wstrb: 0x%02x data: %s",
-                    awid, cur_addr, strb, ' '.join((f'{c:02x}' for c in data)))
+                if self.log.isEnabledFor(logging.DEBUG):
+                    self.log.debug("Write word awid: 0x%x addr: 0x%08x wstrb: 0x%02x data: %s",
+                            awid, cur_addr, strb, ' '.join((f'{c:02x}' for c in data)))
 
                 for i in range(self.byte_lanes):
                     if strb & (1 << i):
@@ -246,7 +247,7 @@ class AxiRamRead(Memory, Reset):
             prot = AxiProt(getattr(ar, 'arprot', AxiProt.NONSECURE))
 
             self.log.info("Read burst arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d arprot: %s",
-                arid, addr, length, size, prot)
+                    arid, addr, length, size, prot)
 
             num_bytes = 2**size
             assert 0 < num_bytes <= self.byte_lanes
@@ -281,8 +282,9 @@ class AxiRamRead(Memory, Reset):
 
                 await self.r_channel.send(r)
 
-                self.log.debug("Read word awid: 0x%x addr: 0x%08x data: %s",
-                    arid, cur_addr, ' '.join((f'{c:02x}' for c in data)))
+                if self.log.isEnabledFor(logging.DEBUG):
+                    self.log.debug("Read word awid: 0x%x addr: 0x%08x data: %s",
+                            arid, cur_addr, ' '.join((f'{c:02x}' for c in data)))
 
                 if burst != AxiBurstType.FIXED:
                     cur_addr += num_bytes
diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py
index 257e301..a264f95 100644
--- a/cocotbext/axi/axil_master.py
+++ b/cocotbext/axi/axil_master.py
@@ -222,8 +222,9 @@ class AxiLiteMasterWrite(Reset):
 
             offset = 0
 
-            self.log.info("Write start addr: 0x%08x prot: %s data: %s",
-                cmd.address, cmd.prot, ' '.join((f'{c:02x}' for c in cmd.data)))
+            if self.log.isEnabledFor(logging.INFO):
+                self.log.info("Write start addr: 0x%08x prot: %s data: %s",
+                        cmd.address, cmd.prot, ' '.join((f'{c:02x}' for c in cmd.data)))
 
             for k in range(cycles):
                 start = 0
@@ -271,7 +272,7 @@ class AxiLiteMasterWrite(Reset):
                     resp = cycle_resp
 
             self.log.info("Write complete addr: 0x%08x prot: %s resp: %s length: %d",
-                cmd.address, cmd.prot, resp, cmd.length)
+                    cmd.address, cmd.prot, resp, cmd.length)
 
             write_resp = AxiLiteWriteResp(cmd.address, cmd.length, resp)
 
@@ -450,7 +451,7 @@ class AxiLiteMasterRead(Reset):
             await self.int_read_resp_command_queue.put(resp_cmd)
 
             self.log.info("Read start addr: 0x%08x prot: %s length: %d",
-                cmd.address, cmd.prot, cmd.length)
+                    cmd.address, cmd.prot, cmd.length)
 
             for k in range(cycles):
                 ar = self.ar_channel._transaction_obj()
@@ -493,8 +494,9 @@ class AxiLiteMasterRead(Reset):
                 for j in range(start, stop):
                     data.extend(bytearray([(cycle_data >> j*8) & 0xff]))
 
-            self.log.info("Read complete addr: 0x%08x prot: %s resp: %s data: %s",
-                cmd.address, cmd.prot, resp, ' '.join((f'{c:02x}' for c in data)))
+            if self.log.isEnabledFor(logging.INFO):
+                self.log.info("Read complete addr: 0x%08x prot: %s resp: %s data: %s",
+                        cmd.address, cmd.prot, resp, ' '.join((f'{c:02x}' for c in data)))
 
             read_resp = AxiLiteReadResp(cmd.address, data, resp)
 
diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py
index ce0963b..41d78fa 100644
--- a/cocotbext/axi/axil_ram.py
+++ b/cocotbext/axi/axil_ram.py
@@ -113,8 +113,9 @@ class AxiLiteRamWrite(Memory, Reset):
 
             data = data.to_bytes(self.byte_lanes, 'little')
 
-            self.log.info("Write data awaddr: 0x%08x awprot: %s wstrb: 0x%02x data: %s",
-                addr, prot, strb, ' '.join((f'{c:02x}' for c in data)))
+            if self.log.isEnabledFor(logging.INFO):
+                self.log.info("Write data awaddr: 0x%08x awprot: %s wstrb: 0x%02x data: %s",
+                        addr, prot, strb, ' '.join((f'{c:02x}' for c in data)))
 
             for i in range(self.byte_lanes):
                 if strb & (1 << i):
@@ -204,8 +205,9 @@ class AxiLiteRamRead(Memory, Reset):
 
             await self.r_channel.send(r)
 
-            self.log.info("Read data araddr: 0x%08x arprot: %s data: %s",
-                addr, prot, ' '.join((f'{c:02x}' for c in data)))
+            if self.log.isEnabledFor(logging.INFO):
+                self.log.info("Read data araddr: 0x%08x arprot: %s data: %s",
+                        addr, prot, ' '.join((f'{c:02x}' for c in data)))
 
 
 class AxiLiteRam(Memory):