From 43de2ea9b0956df56ec261c3c9453acc981a8e7a Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 9 Nov 2021 00:46:37 -0800 Subject: [PATCH] Use getattr with default value when accessing optional signals --- cocotbext/axi/axi_master.py | 12 ++++++------ cocotbext/axi/axi_ram.py | 26 +++++++++++++++----------- cocotbext/axi/axil_master.py | 4 ++-- cocotbext/axi/axil_ram.py | 6 +++--- 4 files changed, 26 insertions(+), 22 deletions(-) diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py index d65274e..65282e1 100644 --- a/cocotbext/axi/axi_master.py +++ b/cocotbext/axi/axi_master.py @@ -475,7 +475,7 @@ class AxiMasterWrite(Reset): while True: b = await self.b_channel.recv() - bid = int(b.bid) + bid = int(getattr(b, 'bid', 0)) if self.active_id[bid] <= 0: raise Exception(f"Unexpected burst ID {bid}") @@ -491,8 +491,8 @@ class AxiMasterWrite(Reset): for burst_length in cmd.burst_list: b = await context.get_resp() - burst_resp = AxiResp(b.bresp) - burst_user = int(b.buser) + burst_resp = AxiResp(getattr(b, 'bresp', AxiResp.OKAY)) + burst_user = int(getattr(b, 'buser', 0)) if burst_resp != AxiResp.OKAY: resp = burst_resp @@ -811,7 +811,7 @@ class AxiMasterRead(Reset): while True: r = await self.r_channel.recv() - rid = int(r.rid) + rid = int(getattr(r, 'rid', 0)) if cur_rid is not None and cur_rid != rid: raise Exception(f"ID not constant within burst (expected {cur_rid}, got {rid})") @@ -853,8 +853,8 @@ class AxiMasterRead(Reset): for r in burst: cycle_data = int(r.rdata) - cycle_resp = AxiResp(r.rresp) - cycle_user = int(r.ruser) + cycle_resp = AxiResp(getattr(r, "rresp", AxiResp.OKAY)) + cycle_user = int(getattr(r, "ruser", 0)) if cycle_resp != AxiResp.OKAY: resp = cycle_resp diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py index f70aba6..487c399 100644 --- a/cocotbext/axi/axi_ram.py +++ b/cocotbext/axi/axi_ram.py @@ -59,6 +59,8 @@ class AxiRamWrite(Memory, Reset): self.byte_lanes = self.width // self.byte_size self.strb_mask = 2**self.byte_lanes-1 + self.max_burst_size = (self.byte_lanes-1).bit_length() + self.log.info("AXI RAM model configuration:") self.log.info(" Memory size: %d bytes", len(self.mem)) self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) @@ -102,12 +104,12 @@ class AxiRamWrite(Memory, Reset): while True: aw = await self.aw_channel.recv() - awid = int(aw.awid) + awid = int(getattr(aw, 'awid', 0)) addr = int(aw.awaddr) - length = int(aw.awlen) - size = int(aw.awsize) - burst = int(aw.awburst) - prot = AxiProt(int(aw.awprot)) + length = int(getattr(aw, 'awlen', 0)) + size = int(getattr(aw, 'awsize', self.max_burst_size)) + burst = AxiBurstType(getattr(aw, 'awburst', AxiBurstType.INCR)) + prot = AxiProt(getattr(aw, 'awprot', AxiProt.NONSECURE)) self.log.info("Write burst awid: 0x%x awaddr: 0x%08x awlen: %d awsize: %d awprot: %s", awid, addr, length, size, prot) @@ -136,7 +138,7 @@ class AxiRamWrite(Memory, Reset): w = await self.w_channel.recv() data = int(w.wdata) - strb = int(w.wstrb) + strb = int(getattr(w, 'wstrb', self.strb_mask)) last = int(w.wlast) # todo latency @@ -193,6 +195,8 @@ class AxiRamRead(Memory, Reset): self.byte_size = 8 self.byte_lanes = self.width // self.byte_size + self.max_burst_size = (self.byte_lanes-1).bit_length() + self.log.info("AXI RAM model configuration:") self.log.info(" Memory size: %d bytes", len(self.mem)) self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) @@ -234,12 +238,12 @@ class AxiRamRead(Memory, Reset): while True: ar = await self.ar_channel.recv() - arid = int(ar.arid) + arid = int(getattr(ar, 'arid', 0)) addr = int(ar.araddr) - length = int(ar.arlen) - size = int(ar.arsize) - burst = int(ar.arburst) - prot = AxiProt(ar.arprot) + length = int(getattr(ar, 'arlen', 0)) + size = int(getattr(ar, 'arsize', self.max_burst_size)) + burst = AxiBurstType(getattr(ar, 'arburst', AxiBurstType.INCR)) + prot = AxiProt(getattr(ar, 'arprot', AxiProt.NONSECURE)) self.log.info("Read burst arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d arprot: %s", arid, addr, length, size, prot) diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py index 03ba7ca..257e301 100644 --- a/cocotbext/axi/axil_master.py +++ b/cocotbext/axi/axil_master.py @@ -265,7 +265,7 @@ class AxiLiteMasterWrite(Reset): for k in range(cmd.cycles): b = await self.b_channel.recv() - cycle_resp = AxiResp(b.bresp) + cycle_resp = AxiResp(getattr(b, 'bresp', AxiResp.OKAY)) if cycle_resp != AxiResp.OKAY: resp = cycle_resp @@ -477,7 +477,7 @@ class AxiLiteMasterRead(Reset): r = await self.r_channel.recv() cycle_data = int(r.rdata) - cycle_resp = AxiResp(r.rresp) + cycle_resp = AxiResp(getattr(r, 'rresp', AxiResp.OKAY)) if cycle_resp != AxiResp.OKAY: resp = cycle_resp diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py index 2977fb1..ce0963b 100644 --- a/cocotbext/axi/axil_ram.py +++ b/cocotbext/axi/axil_ram.py @@ -100,12 +100,12 @@ class AxiLiteRamWrite(Memory, Reset): aw = await self.aw_channel.recv() addr = (int(aw.awaddr) // self.byte_lanes) * self.byte_lanes - prot = AxiProt(aw.awprot) + prot = AxiProt(getattr(aw, 'awprot', AxiProt.NONSECURE)) w = await self.w_channel.recv() data = int(w.wdata) - strb = int(w.wstrb) + strb = int(getattr(w, 'wstrb', self.strb_mask)) # todo latency @@ -190,7 +190,7 @@ class AxiLiteRamRead(Memory, Reset): ar = await self.ar_channel.recv() addr = (int(ar.araddr) // self.byte_lanes) * self.byte_lanes - prot = AxiProt(ar.arprot) + prot = AxiProt(getattr(ar, 'arprot', AxiProt.NONSECURE)) # todo latency