From 4abe02086a215c1224a88fb3d21a40b33aec9ef0 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Sat, 14 Nov 2020 22:47:36 -0800
Subject: [PATCH] Add hexdump methods to AXI RAM models

---
 cocotbext/axi/axi_ram.py  | 19 +++++++++++++++++++
 cocotbext/axi/axil_ram.py | 19 +++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py
index 326409c..04281ad 100644
--- a/cocotbext/axi/axi_ram.py
+++ b/cocotbext/axi/axi_ram.py
@@ -31,6 +31,7 @@ from collections import deque
 
 from .constants import *
 from .axi_channels import *
+from .utils import hexdump, hexdump_str
 
 
 class AxiRamWrite(object):
@@ -71,6 +72,12 @@ class AxiRamWrite(object):
         self.mem.seek(address)
         self.mem.write(bytes(data))
 
+    def hexdump(self, address, length, prefix=""):
+        hexdump(self.mem, address, length, prefix=prefix)
+
+    def hexdump_str(self, address, length, prefix=""):
+        return hexdump_str(self.mem, address, length, prefix=prefix)
+
     async def _process_write(self):
         while True:
             await self.aw_channel.wait()
@@ -181,6 +188,12 @@ class AxiRamRead(object):
         self.mem.seek(address)
         self.mem.write(bytes(data))
 
+    def hexdump(self, address, length, prefix=""):
+        hexdump(self.mem, address, length, prefix=prefix)
+
+    def hexdump_str(self, address, length, prefix=""):
+        return hexdump_str(self.mem, address, length, prefix=prefix)
+
     async def _process_read(self):
         while True:
             await self.ar_channel.wait()
@@ -260,3 +273,9 @@ class AxiRam(object):
         self.mem.seek(address)
         self.mem.write(bytes(data))
 
+    def hexdump(self, address, length, prefix=""):
+        hexdump(self.mem, address, length, prefix=prefix)
+
+    def hexdump_str(self, address, length, prefix=""):
+        return hexdump_str(self.mem, address, length, prefix=prefix)
+
diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py
index 06362e5..567f8cc 100644
--- a/cocotbext/axi/axil_ram.py
+++ b/cocotbext/axi/axil_ram.py
@@ -32,6 +32,7 @@ from collections import deque
 
 from .constants import *
 from .axil_channels import *
+from .utils import hexdump, hexdump_str
 
 
 class AxiLiteRamWrite(object):
@@ -70,6 +71,12 @@ class AxiLiteRamWrite(object):
         self.mem.seek(address)
         self.mem.write(bytes(data))
 
+    def hexdump(self, address, length, prefix=""):
+        hexdump(self.mem, address, length, prefix=prefix)
+
+    def hexdump_str(self, address, length, prefix=""):
+        return hexdump_str(self.mem, address, length, prefix=prefix)
+
     async def _process_write(self):
         while True:
             await self.aw_channel.wait()
@@ -140,6 +147,12 @@ class AxiLiteRamRead(object):
         self.mem.seek(address)
         self.mem.write(bytes(data))
 
+    def hexdump(self, address, length, prefix=""):
+        hexdump(self.mem, address, length, prefix=prefix)
+
+    def hexdump_str(self, address, length, prefix=""):
+        return hexdump_str(self.mem, address, length, prefix=prefix)
+
     async def _process_read(self):
         while True:
             await self.ar_channel.wait()
@@ -185,3 +198,9 @@ class AxiLiteRam(object):
         self.mem.seek(address)
         self.mem.write(bytes(data))
 
+    def hexdump(self, address, length, prefix=""):
+        hexdump(self.mem, address, length, prefix=prefix)
+
+    def hexdump_str(self, address, length, prefix=""):
+        return hexdump_str(self.mem, address, length, prefix=prefix)
+