bslathi19/cocotbext-axi
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Peel off memory interface methods into separate object, add word access wrappers

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This commit is contained in:
Alex Forencich
2020-12-01 22:48:41 -08:00
parent 0bbad73760
commit 645ebb069c
5 changed files with 135 additions and 143 deletions
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10
tests/axi/test_axi.py
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@@ -102,15 +102,15 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None, si
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axi_ram.write_mem(addr-128, b'\xaa'*(length+256))
tb.axi_ram.write(addr-128, b'\xaa'*(length+256))
await tb.axi_master.write(addr, test_data, size=size)
tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & 0xfffffff0)-16, (((addr & 0xf)+length-1) & 0xfffffff0)+48))
assert tb.axi_ram.read_mem(addr, length) == test_data
assert tb.axi_ram.read_mem(addr-1, 1) == b'\xaa'
assert tb.axi_ram.read_mem(addr+length, 1) == b'\xaa'
assert tb.axi_ram.read(addr, length) == test_data
assert tb.axi_ram.read(addr-1, 1) == b'\xaa'
assert tb.axi_ram.read(addr+length, 1) == b'\xaa'
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
@@ -137,7 +137,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None, siz
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axi_ram.write_mem(addr, test_data)
tb.axi_ram.write(addr, test_data)
data = await tb.axi_master.read(addr, length, size=size)

10
tests/axil/test_axil.py
View File

@@ -95,15 +95,15 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axil_ram.write_mem(addr-128, b'\xaa'*(length+256))
tb.axil_ram.write(addr-128, b'\xaa'*(length+256))
await tb.axil_master.write(addr, test_data)
tb.log.debug("%s", tb.axil_ram.hexdump_str((addr & 0xfffffff0)-16, (((addr & 0xf)+length-1) & 0xfffffff0)+48))
assert tb.axil_ram.read_mem(addr, length) == test_data
assert tb.axil_ram.read_mem(addr-1, 1) == b'\xaa'
assert tb.axil_ram.read_mem(addr+length, 1) == b'\xaa'
assert tb.axil_ram.read(addr, length) == test_data
assert tb.axil_ram.read(addr-1, 1) == b'\xaa'
assert tb.axil_ram.read(addr+length, 1) == b'\xaa'
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
@@ -126,7 +126,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axil_ram.write_mem(addr, test_data)
tb.axil_ram.write(addr, test_data)
data = await tb.axil_master.read(addr, length)