Peel off memory interface methods into separate object, add word access wrappers
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@@ -102,15 +102,15 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None, si
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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tb.axi_ram.write_mem(addr-128, b'\xaa'*(length+256))
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tb.axi_ram.write(addr-128, b'\xaa'*(length+256))
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await tb.axi_master.write(addr, test_data, size=size)
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tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & 0xfffffff0)-16, (((addr & 0xf)+length-1) & 0xfffffff0)+48))
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assert tb.axi_ram.read_mem(addr, length) == test_data
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assert tb.axi_ram.read_mem(addr-1, 1) == b'\xaa'
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assert tb.axi_ram.read_mem(addr+length, 1) == b'\xaa'
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assert tb.axi_ram.read(addr, length) == test_data
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assert tb.axi_ram.read(addr-1, 1) == b'\xaa'
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assert tb.axi_ram.read(addr+length, 1) == b'\xaa'
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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@@ -137,7 +137,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None, siz
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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tb.axi_ram.write_mem(addr, test_data)
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tb.axi_ram.write(addr, test_data)
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data = await tb.axi_master.read(addr, length, size=size)
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