diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py
index 4b7c61a..50894a5 100644
--- a/cocotbext/axi/axi_master.py
+++ b/cocotbext/axi/axi_master.py
@@ -59,8 +59,11 @@ class AxiMasterWrite(Reset):
         self.log.info("https://github.com/alexforencich/cocotbext-axi")
 
         self.aw_channel = AxiAWSource(bus.aw, clock, reset, reset_active_level)
+        self.aw_channel.queue_occupancy_limit = 2
         self.w_channel = AxiWSource(bus.w, clock, reset, reset_active_level)
+        self.w_channel.queue_occupancy_limit = 2
         self.b_channel = AxiBSink(bus.b, clock, reset, reset_active_level)
+        self.b_channel.queue_occupancy_limit = 2
 
         self.write_command_queue = Queue()
         self.current_write_command = None
@@ -426,7 +429,9 @@ class AxiMasterRead(Reset):
         self.log.info("https://github.com/alexforencich/cocotbext-axi")
 
         self.ar_channel = AxiARSource(bus.ar, clock, reset, reset_active_level)
+        self.ar_channel.queue_occupancy_limit = 2
         self.r_channel = AxiRSink(bus.r, clock, reset, reset_active_level)
+        self.r_channel.queue_occupancy_limit = 2
 
         self.read_command_queue = Queue()
         self.current_read_command = None
diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py
index ec35ee6..e8c7d58 100644
--- a/cocotbext/axi/axi_ram.py
+++ b/cocotbext/axi/axi_ram.py
@@ -45,8 +45,11 @@ class AxiRamWrite(Memory, Reset):
         super().__init__(size, mem, *args, **kwargs)
 
         self.aw_channel = AxiAWSink(bus.aw, clock, reset, reset_active_level)
+        self.aw_channel.queue_occupancy_limit = 2
         self.w_channel = AxiWSink(bus.w, clock, reset, reset_active_level)
+        self.w_channel.queue_occupancy_limit = 2
         self.b_channel = AxiBSource(bus.b, clock, reset, reset_active_level)
+        self.b_channel.queue_occupancy_limit = 2
 
         self.width = len(self.w_channel.bus.wdata)
         self.byte_size = 8
@@ -168,7 +171,9 @@ class AxiRamRead(Memory, Reset):
         super().__init__(size, mem, *args, **kwargs)
 
         self.ar_channel = AxiARSink(bus.ar, clock, reset, reset_active_level)
+        self.ar_channel.queue_occupancy_limit = 2
         self.r_channel = AxiRSource(bus.r, clock, reset, reset_active_level)
+        self.r_channel.queue_occupancy_limit = 2
 
         self.width = len(self.r_channel.bus.rdata)
         self.byte_size = 8
diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py
index 8abe825..b6b3425 100644
--- a/cocotbext/axi/axil_master.py
+++ b/cocotbext/axi/axil_master.py
@@ -55,8 +55,11 @@ class AxiLiteMasterWrite(Reset):
         self.log.info("https://github.com/alexforencich/cocotbext-axi")
 
         self.aw_channel = AxiLiteAWSource(bus.aw, clock, reset, reset_active_level)
+        self.aw_channel.queue_occupancy_limit = 2
         self.w_channel = AxiLiteWSource(bus.w, clock, reset, reset_active_level)
+        self.w_channel.queue_occupancy_limit = 2
         self.b_channel = AxiLiteBSink(bus.b, clock, reset, reset_active_level)
+        self.b_channel.queue_occupancy_limit = 2
 
         self.write_command_queue = Queue()
         self.current_write_command = None
@@ -276,7 +279,9 @@ class AxiLiteMasterRead(Reset):
         self.log.info("https://github.com/alexforencich/cocotbext-axi")
 
         self.ar_channel = AxiLiteARSource(bus.ar, clock, reset, reset_active_level)
+        self.ar_channel.queue_occupancy_limit = 2
         self.r_channel = AxiLiteRSink(bus.r, clock, reset, reset_active_level)
+        self.r_channel.queue_occupancy_limit = 2
 
         self.read_command_queue = Queue()
         self.current_read_command = None
diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py
index c50ff76..77c5668 100644
--- a/cocotbext/axi/axil_ram.py
+++ b/cocotbext/axi/axil_ram.py
@@ -45,8 +45,11 @@ class AxiLiteRamWrite(Memory, Reset):
         super().__init__(size, mem, *args, **kwargs)
 
         self.aw_channel = AxiLiteAWSink(bus.aw, clock, reset, reset_active_level)
+        self.aw_channel.queue_occupancy_limit = 2
         self.w_channel = AxiLiteWSink(bus.w, clock, reset, reset_active_level)
+        self.w_channel.queue_occupancy_limit = 2
         self.b_channel = AxiLiteBSource(bus.b, clock, reset, reset_active_level)
+        self.b_channel.queue_occupancy_limit = 2
 
         self.width = len(self.w_channel.bus.wdata)
         self.byte_size = 8
@@ -126,7 +129,9 @@ class AxiLiteRamRead(Memory, Reset):
         super().__init__(size, mem, *args, **kwargs)
 
         self.ar_channel = AxiLiteARSink(bus.ar, clock, reset, reset_active_level)
+        self.ar_channel.queue_occupancy_limit = 2
         self.r_channel = AxiLiteRSource(bus.r, clock, reset, reset_active_level)
+        self.r_channel.queue_occupancy_limit = 2
 
         self.width = len(self.r_channel.bus.rdata)
         self.byte_size = 8