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Reset processing on assert edge only to permit operations to be queued while reset is asserted

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This commit is contained in:
Alex Forencich
2021-03-21 12:13:19 -07:00
parent 156fada616
commit 7fb8c4e28b
6 changed files with 187 additions and 183 deletions
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14
cocotbext/axi/axil_ram.py
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@@ -72,15 +72,15 @@ class AxiLiteRamWrite(Memory, Reset):
if self._process_write_cr is not None:
self._process_write_cr.kill()
self._process_write_cr = None
self.aw_channel.clear()
self.w_channel.clear()
self.b_channel.clear()
else:
self.log.info("Reset de-asserted")
if self._process_write_cr is None:
self._process_write_cr = cocotb.scheduler.start_soon(self._process_write())
self.aw_channel.clear()
self.w_channel.clear()
self.b_channel.clear()
async def _process_write(self):
while True:
aw = await self.aw_channel.recv()
@@ -150,14 +150,14 @@ class AxiLiteRamRead(Memory, Reset):
if self._process_read_cr is not None:
self._process_read_cr.kill()
self._process_read_cr = None
self.ar_channel.clear()
self.r_channel.clear()
else:
self.log.info("Reset de-asserted")
if self._process_read_cr is None:
self._process_read_cr = cocotb.scheduler.start_soon(self._process_read())
self.ar_channel.clear()
self.r_channel.clear()
async def _process_read(self):
while True:
ar = await self.ar_channel.recv()