diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py index 8227b37..553a927 100644 --- a/cocotbext/axi/axi_master.py +++ b/cocotbext/axi/axi_master.py @@ -166,23 +166,23 @@ class AxiMasterWrite(Reset): self.width = len(self.w_channel.bus.wdata) self.byte_size = 8 - self.byte_width = self.width // self.byte_size - self.strb_mask = 2**self.byte_width-1 + self.byte_lanes = self.width // self.byte_size + self.strb_mask = 2**self.byte_lanes-1 self.max_burst_len = max(min(max_burst_len, 256), 1) - self.max_burst_size = (self.byte_width-1).bit_length() + self.max_burst_size = (self.byte_lanes-1).bit_length() self.log.info("AXI master configuration:") self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid)) self.log.info(" Byte size: %d bits", self.byte_size) - self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) self.log.info(" Max burst size: %d (%d bytes)", self.max_burst_size, 2**self.max_burst_size) self.log.info(" Max burst length: %d cycles (%d bytes)", - self.max_burst_len, self.max_burst_len*self.byte_width) + self.max_burst_len, self.max_burst_len*self.byte_lanes) - assert self.byte_width == len(self.w_channel.bus.wstrb) - assert self.byte_width * self.byte_size == self.width + assert self.byte_lanes == len(self.w_channel.bus.wstrb) + assert self.byte_lanes * self.byte_size == self.width assert len(self.b_channel.bus.bid) == len(self.aw_channel.bus.awid) @@ -332,10 +332,10 @@ class AxiMasterWrite(Reset): num_bytes = 2**cmd.size aligned_addr = (cmd.address // num_bytes) * num_bytes - word_addr = (cmd.address // self.byte_width) * self.byte_width + word_addr = (cmd.address // self.byte_lanes) * self.byte_lanes - start_offset = cmd.address % self.byte_width - end_offset = ((cmd.address + len(cmd.data) - 1) % self.byte_width) + 1 + start_offset = cmd.address % self.byte_lanes + end_offset = ((cmd.address + len(cmd.data) - 1) % self.byte_lanes) + 1 cycles = (len(cmd.data) + (cmd.address % num_bytes) + num_bytes-1) // num_bytes @@ -368,7 +368,7 @@ class AxiMasterWrite(Reset): if k == cycles-1: stop = end_offset - strb = (self.strb_mask << start) & self.strb_mask & (self.strb_mask >> (self.byte_width - stop)) + strb = (self.strb_mask << start) & self.strb_mask & (self.strb_mask >> (self.byte_lanes - stop)) val = 0 for j in range(start, stop): @@ -423,7 +423,7 @@ class AxiMasterWrite(Reset): await self.w_channel.send(w) cur_addr += num_bytes - cycle_offset = (cycle_offset + num_bytes) % self.byte_width + cycle_offset = (cycle_offset + num_bytes) % self.byte_lanes resp_cmd = AxiWriteRespCmd(cmd.address, len(cmd.data), cmd.size, cycles, cmd.prot, burst_list, cmd.event) self.tag_context_manager.start_cmd(awid, resp_cmd) @@ -508,21 +508,21 @@ class AxiMasterRead(Reset): self.width = len(self.r_channel.bus.rdata) self.byte_size = 8 - self.byte_width = self.width // self.byte_size + self.byte_lanes = self.width // self.byte_size self.max_burst_len = max(min(max_burst_len, 256), 1) - self.max_burst_size = (self.byte_width-1).bit_length() + self.max_burst_size = (self.byte_lanes-1).bit_length() self.log.info("AXI master configuration:") self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid)) self.log.info(" Byte size: %d bits", self.byte_size) - self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) self.log.info(" Max burst size: %d (%d bytes)", self.max_burst_size, 2**self.max_burst_size) self.log.info(" Max burst length: %d cycles (%d bytes)", - self.max_burst_len, self.max_burst_len*self.byte_width) + self.max_burst_len, self.max_burst_len*self.byte_lanes) - assert self.byte_width * self.byte_size == self.width + assert self.byte_lanes * self.byte_size == self.width assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid) @@ -752,9 +752,9 @@ class AxiMasterRead(Reset): num_bytes = 2**cmd.size aligned_addr = (cmd.address // num_bytes) * num_bytes - word_addr = (cmd.address // self.byte_width) * self.byte_width + word_addr = (cmd.address // self.byte_lanes) * self.byte_lanes - start_offset = cmd.address % self.byte_width + start_offset = cmd.address % self.byte_lanes cycle_offset = aligned_addr - word_addr data = bytearray() @@ -790,7 +790,7 @@ class AxiMasterRead(Reset): for j in range(start, stop): data.append((cycle_data >> j*8) & 0xff) - cycle_offset = (cycle_offset + num_bytes) % self.byte_width + cycle_offset = (cycle_offset + num_bytes) % self.byte_lanes first = False diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py index e8c7d58..3686d9f 100644 --- a/cocotbext/axi/axi_ram.py +++ b/cocotbext/axi/axi_ram.py @@ -53,18 +53,18 @@ class AxiRamWrite(Memory, Reset): self.width = len(self.w_channel.bus.wdata) self.byte_size = 8 - self.byte_width = self.width // self.byte_size - self.strb_mask = 2**self.byte_width-1 + self.byte_lanes = self.width // self.byte_size + self.strb_mask = 2**self.byte_lanes-1 self.log.info("AXI RAM model configuration:") self.log.info(" Memory size: %d bytes", len(self.mem)) self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid)) self.log.info(" Byte size: %d bits", self.byte_size) - self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) - assert self.byte_width == len(self.w_channel.bus.wstrb) - assert self.byte_width * self.byte_size == self.width + assert self.byte_lanes == len(self.w_channel.bus.wstrb) + assert self.byte_lanes * self.byte_size == self.width assert len(self.b_channel.bus.bid) == len(self.aw_channel.bus.awid) @@ -102,7 +102,7 @@ class AxiRamWrite(Memory, Reset): awid, addr, length, size, prot) num_bytes = 2**size - assert 0 < num_bytes <= self.byte_width + assert 0 < num_bytes <= self.byte_lanes aligned_addr = (addr // num_bytes) * num_bytes length += 1 @@ -120,7 +120,7 @@ class AxiRamWrite(Memory, Reset): cur_addr = aligned_addr for n in range(length): - cur_word_addr = (cur_addr // self.byte_width) * self.byte_width + cur_word_addr = (cur_addr // self.byte_lanes) * self.byte_lanes w = await self.w_channel.recv() @@ -132,12 +132,12 @@ class AxiRamWrite(Memory, Reset): self.mem.seek(cur_word_addr % self.size) - data = data.to_bytes(self.byte_width, 'little') + data = data.to_bytes(self.byte_lanes, 'little') self.log.debug("Write word awid: 0x%x addr: 0x%08x wstrb: 0x%02x data: %s", awid, cur_addr, strb, ' '.join((f'{c:02x}' for c in data))) - for i in range(self.byte_width): + for i in range(self.byte_lanes): if strb & (1 << i): self.mem.write(data[i:i+1]) else: @@ -177,16 +177,16 @@ class AxiRamRead(Memory, Reset): self.width = len(self.r_channel.bus.rdata) self.byte_size = 8 - self.byte_width = self.width // self.byte_size + self.byte_lanes = self.width // self.byte_size self.log.info("AXI RAM model configuration:") self.log.info(" Memory size: %d bytes", len(self.mem)) self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid)) self.log.info(" Byte size: %d bits", self.byte_size) - self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) - assert self.byte_width * self.byte_size == self.width + assert self.byte_lanes * self.byte_size == self.width assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid) @@ -223,7 +223,7 @@ class AxiRamRead(Memory, Reset): arid, addr, length, size, prot) num_bytes = 2**size - assert 0 < num_bytes <= self.byte_width + assert 0 < num_bytes <= self.byte_lanes aligned_addr = (addr // num_bytes) * num_bytes length += 1 @@ -241,11 +241,11 @@ class AxiRamRead(Memory, Reset): cur_addr = aligned_addr for n in range(length): - cur_word_addr = (cur_addr // self.byte_width) * self.byte_width + cur_word_addr = (cur_addr // self.byte_lanes) * self.byte_lanes self.mem.seek(cur_word_addr % self.size) - data = self.mem.read(self.byte_width) + data = self.mem.read(self.byte_lanes) r = self.r_channel._transaction_obj() r.rid = arid diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py index b6b3425..cf327ce 100644 --- a/cocotbext/axi/axil_master.py +++ b/cocotbext/axi/axil_master.py @@ -73,16 +73,16 @@ class AxiLiteMasterWrite(Reset): self.width = len(self.w_channel.bus.wdata) self.byte_size = 8 - self.byte_width = self.width // self.byte_size - self.strb_mask = 2**self.byte_width-1 + self.byte_lanes = self.width // self.byte_size + self.strb_mask = 2**self.byte_lanes-1 self.log.info("AXI lite master configuration:") self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) self.log.info(" Byte size: %d bits", self.byte_size) - self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) - assert self.byte_width == len(self.w_channel.bus.wstrb) - assert self.byte_width * self.byte_size == self.width + assert self.byte_lanes == len(self.w_channel.bus.wstrb) + assert self.byte_lanes * self.byte_size == self.width self._process_write_cr = None self._process_write_resp_cr = None @@ -191,15 +191,15 @@ class AxiLiteMasterWrite(Reset): cmd = await self.write_command_queue.get() self.current_write_command = cmd - word_addr = (cmd.address // self.byte_width) * self.byte_width + word_addr = (cmd.address // self.byte_lanes) * self.byte_lanes - start_offset = cmd.address % self.byte_width - end_offset = ((cmd.address + len(cmd.data) - 1) % self.byte_width) + 1 + start_offset = cmd.address % self.byte_lanes + end_offset = ((cmd.address + len(cmd.data) - 1) % self.byte_lanes) + 1 strb_start = (self.strb_mask << start_offset) & self.strb_mask - strb_end = self.strb_mask >> (self.byte_width - end_offset) + strb_end = self.strb_mask >> (self.byte_lanes - end_offset) - cycles = (len(cmd.data) + (cmd.address % self.byte_width) + self.byte_width-1) // self.byte_width + cycles = (len(cmd.data) + (cmd.address % self.byte_lanes) + self.byte_lanes-1) // self.byte_lanes resp_cmd = AxiLiteWriteRespCmd(cmd.address, len(cmd.data), cycles, cmd.prot, cmd.event) await self.int_write_resp_command_queue.put(resp_cmd) @@ -211,7 +211,7 @@ class AxiLiteMasterWrite(Reset): for k in range(cycles): start = 0 - stop = self.byte_width + stop = self.byte_lanes strb = self.strb_mask if k == 0: @@ -227,7 +227,7 @@ class AxiLiteMasterWrite(Reset): offset += 1 aw = self.aw_channel._transaction_obj() - aw.awaddr = word_addr + k*self.byte_width + aw.awaddr = word_addr + k*self.byte_lanes aw.awprot = cmd.prot w = self.w_channel._transaction_obj() @@ -295,14 +295,14 @@ class AxiLiteMasterRead(Reset): self.width = len(self.r_channel.bus.rdata) self.byte_size = 8 - self.byte_width = self.width // self.byte_size + self.byte_lanes = self.width // self.byte_size self.log.info("AXI lite master configuration:") self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) self.log.info(" Byte size: %d bits", self.byte_size) - self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) - assert self.byte_width * self.byte_size == self.width + assert self.byte_lanes * self.byte_size == self.width self._process_read_cr = None self._process_read_resp_cr = None @@ -410,9 +410,9 @@ class AxiLiteMasterRead(Reset): cmd = await self.read_command_queue.get() self.current_read_command = cmd - word_addr = (cmd.address // self.byte_width) * self.byte_width + word_addr = (cmd.address // self.byte_lanes) * self.byte_lanes - cycles = (cmd.length + self.byte_width-1 + (cmd.address % self.byte_width)) // self.byte_width + cycles = (cmd.length + self.byte_lanes-1 + (cmd.address % self.byte_lanes)) // self.byte_lanes resp_cmd = AxiLiteReadRespCmd(cmd.address, cmd.length, cycles, cmd.prot, cmd.event) await self.int_read_resp_command_queue.put(resp_cmd) @@ -422,7 +422,7 @@ class AxiLiteMasterRead(Reset): for k in range(cycles): ar = self.ar_channel._transaction_obj() - ar.araddr = word_addr + k*self.byte_width + ar.araddr = word_addr + k*self.byte_lanes ar.arprot = cmd.prot await self.ar_channel.send(ar) @@ -434,8 +434,8 @@ class AxiLiteMasterRead(Reset): cmd = await self.int_read_resp_command_queue.get() self.current_read_resp_command = cmd - start_offset = cmd.address % self.byte_width - end_offset = ((cmd.address + cmd.length - 1) % self.byte_width) + 1 + start_offset = cmd.address % self.byte_lanes + end_offset = ((cmd.address + cmd.length - 1) % self.byte_lanes) + 1 data = bytearray() @@ -451,7 +451,7 @@ class AxiLiteMasterRead(Reset): resp = cycle_resp start = 0 - stop = self.byte_width + stop = self.byte_lanes if k == 0: start = start_offset diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py index 77c5668..f7979f8 100644 --- a/cocotbext/axi/axil_ram.py +++ b/cocotbext/axi/axil_ram.py @@ -53,17 +53,17 @@ class AxiLiteRamWrite(Memory, Reset): self.width = len(self.w_channel.bus.wdata) self.byte_size = 8 - self.byte_width = self.width // self.byte_size - self.strb_mask = 2**self.byte_width-1 + self.byte_lanes = self.width // self.byte_size + self.strb_mask = 2**self.byte_lanes-1 self.log.info("AXI lite RAM model configuration:") self.log.info(" Memory size: %d bytes", len(self.mem)) self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) self.log.info(" Byte size: %d bits", self.byte_size) - self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) - assert self.byte_width == len(self.w_channel.bus.wstrb) - assert self.byte_width * self.byte_size == self.width + assert self.byte_lanes == len(self.w_channel.bus.wstrb) + assert self.byte_lanes * self.byte_size == self.width self._process_write_cr = None @@ -88,7 +88,7 @@ class AxiLiteRamWrite(Memory, Reset): while True: aw = await self.aw_channel.recv() - addr = (int(aw.awaddr) // self.byte_width) * self.byte_width + addr = (int(aw.awaddr) // self.byte_lanes) * self.byte_lanes prot = AxiProt(aw.awprot) w = await self.w_channel.recv() @@ -100,12 +100,12 @@ class AxiLiteRamWrite(Memory, Reset): self.mem.seek(addr % self.size) - data = data.to_bytes(self.byte_width, 'little') + data = data.to_bytes(self.byte_lanes, 'little') self.log.info("Write data awaddr: 0x%08x awprot: %s wstrb: 0x%02x data: %s", addr, prot, strb, ' '.join((f'{c:02x}' for c in data))) - for i in range(self.byte_width): + for i in range(self.byte_lanes): if strb & (1 << i): self.mem.write(data[i:i+1]) else: @@ -135,15 +135,15 @@ class AxiLiteRamRead(Memory, Reset): self.width = len(self.r_channel.bus.rdata) self.byte_size = 8 - self.byte_width = self.width // self.byte_size + self.byte_lanes = self.width // self.byte_size self.log.info("AXI lite RAM model configuration:") self.log.info(" Memory size: %d bytes", len(self.mem)) self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) self.log.info(" Byte size: %d bits", self.byte_size) - self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) - assert self.byte_width * self.byte_size == self.width + assert self.byte_lanes * self.byte_size == self.width self._process_read_cr = None @@ -167,14 +167,14 @@ class AxiLiteRamRead(Memory, Reset): while True: ar = await self.ar_channel.recv() - addr = (int(ar.araddr) // self.byte_width) * self.byte_width + addr = (int(ar.araddr) // self.byte_lanes) * self.byte_lanes prot = AxiProt(ar.arprot) # todo latency self.mem.seek(addr % self.size) - data = self.mem.read(self.byte_width) + data = self.mem.read(self.byte_lanes) r = self.r_channel._transaction_obj() r.rdata = int.from_bytes(data, 'little') diff --git a/tests/axi/test_axi.py b/tests/axi/test_axi.py index 82b14cc..e6f2e01 100644 --- a/tests/axi/test_axi.py +++ b/tests/axi/test_axi.py @@ -85,7 +85,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None, si tb = TB(dut) - byte_width = tb.axi_master.write_if.byte_width + byte_lanes = tb.axi_master.write_if.byte_lanes max_burst_size = tb.axi_master.write_if.max_burst_size if size is None: @@ -96,8 +96,8 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None, si tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) - for length in list(range(1, byte_width*2))+[1024]: - for offset in list(range(byte_width))+list(range(4096-byte_width, 4096)): + for length in list(range(1, byte_lanes*2))+[1024]: + for offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)): tb.log.info("length %d, offset %d", length, offset) addr = offset+0x1000 test_data = bytearray([x % 256 for x in range(length)]) @@ -120,7 +120,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None, siz tb = TB(dut) - byte_width = tb.axi_master.write_if.byte_width + byte_lanes = tb.axi_master.write_if.byte_lanes max_burst_size = tb.axi_master.write_if.max_burst_size if size is None: @@ -131,8 +131,8 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None, siz tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) - for length in list(range(1, byte_width*2))+[1024]: - for offset in list(range(byte_width))+list(range(4096-byte_width, 4096)): + for length in list(range(1, byte_lanes*2))+[1024]: + for offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)): tb.log.info("length %d, offset %d", length, offset) addr = offset+0x1000 test_data = bytearray([x % 256 for x in range(length)]) @@ -151,12 +151,12 @@ async def run_test_write_words(dut): tb = TB(dut) - byte_width = tb.axi_master.write_if.byte_width + byte_lanes = tb.axi_master.write_if.byte_lanes await tb.cycle_reset() for length in list(range(1, 4)): - for offset in list(range(byte_width)): + for offset in list(range(byte_lanes)): tb.log.info("length %d, offset %d", length, offset) addr = offset+0x1000 @@ -205,12 +205,12 @@ async def run_test_read_words(dut): tb = TB(dut) - byte_width = tb.axi_master.write_if.byte_width + byte_lanes = tb.axi_master.write_if.byte_lanes await tb.cycle_reset() for length in list(range(1, 4)): - for offset in list(range(byte_width)): + for offset in list(range(byte_lanes)): tb.log.info("length %d, offset %d", length, offset) addr = offset+0x1000 @@ -299,8 +299,8 @@ def cycle_pause(): if cocotb.SIM_NAME: data_width = len(cocotb.top.axi_wdata) - byte_width = data_width // 8 - max_burst_size = (byte_width-1).bit_length() + byte_lanes = data_width // 8 + max_burst_size = (byte_lanes-1).bit_length() for test in [run_test_write, run_test_read]: diff --git a/tests/axil/test_axil.py b/tests/axil/test_axil.py index 022041d..cf16918 100644 --- a/tests/axil/test_axil.py +++ b/tests/axil/test_axil.py @@ -82,15 +82,15 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins tb = TB(dut) - byte_width = tb.axil_master.write_if.byte_width + byte_lanes = tb.axil_master.write_if.byte_lanes await tb.cycle_reset() tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) - for length in range(1, byte_width*2): - for offset in range(byte_width): + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): tb.log.info("length %d, offset %d", length, offset) addr = offset+0x1000 test_data = bytearray([x % 256 for x in range(length)]) @@ -113,15 +113,15 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse tb = TB(dut) - byte_width = tb.axil_master.write_if.byte_width + byte_lanes = tb.axil_master.write_if.byte_lanes await tb.cycle_reset() tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) - for length in range(1, byte_width*2): - for offset in range(byte_width): + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): tb.log.info("length %d, offset %d", length, offset) addr = offset+0x1000 test_data = bytearray([x % 256 for x in range(length)]) @@ -140,12 +140,12 @@ async def run_test_write_words(dut): tb = TB(dut) - byte_width = tb.axil_master.write_if.byte_width + byte_lanes = tb.axil_master.write_if.byte_lanes await tb.cycle_reset() for length in list(range(1, 4)): - for offset in list(range(byte_width)): + for offset in list(range(byte_lanes)): tb.log.info("length %d, offset %d", length, offset) addr = offset+0x1000 @@ -194,12 +194,12 @@ async def run_test_read_words(dut): tb = TB(dut) - byte_width = tb.axil_master.write_if.byte_width + byte_lanes = tb.axil_master.write_if.byte_lanes await tb.cycle_reset() for length in list(range(1, 4)): - for offset in list(range(byte_width)): + for offset in list(range(byte_lanes)): tb.log.info("length %d, offset %d", length, offset) addr = offset+0x1000