diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py
index 553a927..12026bb 100644
--- a/cocotbext/axi/axi_master.py
+++ b/cocotbext/axi/axi_master.py
@@ -137,6 +137,9 @@ class TagContextManager:
 
 class AxiMasterWrite(Reset):
     def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_len=256):
+        self.bus = bus
+        self.clock = clock
+        self.reset = reset
         self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
 
         self.log.info("AXI master (write)")
@@ -481,6 +484,9 @@ class AxiMasterWrite(Reset):
 
 class AxiMasterRead(Reset):
     def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_len=256):
+        self.bus = bus
+        self.clock = clock
+        self.reset = reset
         self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
 
         self.log.info("AXI master (read)")
diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py
index 3686d9f..df6d486 100644
--- a/cocotbext/axi/axi_ram.py
+++ b/cocotbext/axi/axi_ram.py
@@ -35,6 +35,9 @@ from .reset import Reset
 
 class AxiRamWrite(Memory, Reset):
     def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
+        self.bus = bus
+        self.clock = clock
+        self.reset = reset
         self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
 
         self.log.info("AXI RAM model (write)")
@@ -161,6 +164,9 @@ class AxiRamWrite(Memory, Reset):
 
 class AxiRamRead(Memory, Reset):
     def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
+        self.bus = bus
+        self.clock = clock
+        self.reset = reset
         self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
 
         self.log.info("AXI RAM model (read)")
diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py
index cf327ce..f77678b 100644
--- a/cocotbext/axi/axil_master.py
+++ b/cocotbext/axi/axil_master.py
@@ -47,6 +47,9 @@ AxiLiteReadResp = namedtuple("AxiLiteReadResp", ["address", "data", "resp"])
 
 class AxiLiteMasterWrite(Reset):
     def __init__(self, bus, clock, reset=None, reset_active_level=True):
+        self.bus = bus
+        self.clock = clock
+        self.reset = reset
         self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
 
         self.log.info("AXI lite master (write)")
@@ -271,6 +274,9 @@ class AxiLiteMasterWrite(Reset):
 
 class AxiLiteMasterRead(Reset):
     def __init__(self, bus, clock, reset=None, reset_active_level=True):
+        self.bus = bus
+        self.clock = clock
+        self.reset = reset
         self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
 
         self.log.info("AXI lite master (read)")
diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py
index f7979f8..29f3fcf 100644
--- a/cocotbext/axi/axil_ram.py
+++ b/cocotbext/axi/axil_ram.py
@@ -35,6 +35,9 @@ from .reset import Reset
 
 class AxiLiteRamWrite(Memory, Reset):
     def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
+        self.bus = bus
+        self.clock = clock
+        self.reset = reset
         self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
 
         self.log.info("AXI lite RAM model (write)")
@@ -119,6 +122,9 @@ class AxiLiteRamWrite(Memory, Reset):
 
 class AxiLiteRamRead(Memory, Reset):
     def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
+        self.bus = bus
+        self.clock = clock
+        self.reset = reset
         self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
 
         self.log.info("AXI lite RAM model (read)")