diff --git a/cocotbext/axi/__init__.py b/cocotbext/axi/__init__.py
index b6b4e36..9c247cf 100644
--- a/cocotbext/axi/__init__.py
+++ b/cocotbext/axi/__init__.py
@@ -22,6 +22,8 @@ THE SOFTWARE.
 
 """
 
+from .version import __version__
+
 from .constants import *
 
 from .axis import AxiStreamFrame, AxiStreamSource, AxiStreamSink
diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py
index 9506c56..9a6f77c 100644
--- a/cocotbext/axi/axi_master.py
+++ b/cocotbext/axi/axi_master.py
@@ -28,6 +28,7 @@ from cocotb.log import SimLog
 
 from collections import deque
 
+from .version import __version__
 from .constants import *
 from .axi_channels import *
 
@@ -36,6 +37,11 @@ class AxiMasterWrite(object):
     def __init__(self, entity, name, clock, reset=None):
         self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
 
+        self.log.info("AXI master model")
+        self.log.info("cocotbext-axi version %s", __version__)
+        self.log.info("Copyright (c) 2020 Alex Forencich")
+        self.log.info("https://github.com/alexforencich/cocotbext-axi")
+
         self.reset = reset
 
         self.aw_channel = AxiAWSource(entity, name, clock, reset)
diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py
index 38e4714..04dd08f 100644
--- a/cocotbext/axi/axi_ram.py
+++ b/cocotbext/axi/axi_ram.py
@@ -29,6 +29,7 @@ from cocotb.log import SimLog
 import mmap
 from collections import deque
 
+from .version import __version__
 from .constants import *
 from .axi_channels import *
 from .utils import hexdump, hexdump_str
@@ -38,6 +39,11 @@ class AxiRamWrite(object):
     def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
         self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
 
+        self.log.info("AXI RAM model")
+        self.log.info("cocotbext-axi version %s", __version__)
+        self.log.info("Copyright (c) 2020 Alex Forencich")
+        self.log.info("https://github.com/alexforencich/cocotbext-axi")
+
         if type(mem) is mmap.mmap:
             self.mem = mem
         else:
diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py
index 41f7eab..13a1f71 100644
--- a/cocotbext/axi/axil_master.py
+++ b/cocotbext/axi/axil_master.py
@@ -28,6 +28,7 @@ from cocotb.log import SimLog
 
 from collections import deque
 
+from .version import __version__
 from .constants import *
 from .axil_channels import *
 
@@ -36,6 +37,11 @@ class AxiLiteMasterWrite(object):
     def __init__(self, entity, name, clock, reset=None):
         self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
 
+        self.log.info("AXI lite master model")
+        self.log.info("cocotbext-axi version %s", __version__)
+        self.log.info("Copyright (c) 2020 Alex Forencich")
+        self.log.info("https://github.com/alexforencich/cocotbext-axi")
+
         self.reset = reset
 
         self.aw_channel = AxiLiteAWSource(entity, name, clock, reset)
diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py
index 567f8cc..e74077d 100644
--- a/cocotbext/axi/axil_ram.py
+++ b/cocotbext/axi/axil_ram.py
@@ -30,6 +30,7 @@ import mmap
 import queue
 from collections import deque
 
+from .version import __version__
 from .constants import *
 from .axil_channels import *
 from .utils import hexdump, hexdump_str
@@ -39,6 +40,11 @@ class AxiLiteRamWrite(object):
     def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
         self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
 
+        self.log.info("AXI lite RAM model")
+        self.log.info("cocotbext-axi version %s", __version__)
+        self.log.info("Copyright (c) 2020 Alex Forencich")
+        self.log.info("https://github.com/alexforencich/cocotbext-axi")
+
         if type(mem) is mmap.mmap:
             self.mem = mem
         else:
diff --git a/cocotbext/axi/axis.py b/cocotbext/axi/axis.py
index 7a7cf26..61a9f69 100644
--- a/cocotbext/axi/axis.py
+++ b/cocotbext/axi/axis.py
@@ -29,6 +29,8 @@ from cocotb.log import SimLog
 
 from collections import deque
 
+from .version import __version__
+
 class AxiStreamFrame(object):
     def __init__(self, tdata=b'', tkeep=None, tid=None, tdest=None, tuser=None):
         self.tdata = bytearray()
@@ -218,6 +220,11 @@ class AxiStreamSource(object):
         self.reset = reset
         self.bus = Bus(self.entity, name, self._signals, optional_signals=self._optional_signals, **kwargs)
 
+        self.log.info("AXI stream source")
+        self.log.info("cocotbext-axi version %s", __version__)
+        self.log.info("Copyright (c) 2020 Alex Forencich")
+        self.log.info("https://github.com/alexforencich/cocotbext-axi")
+
         super().__init__(*args, **kwargs)
 
         self.active = False
@@ -389,6 +396,11 @@ class AxiStreamSink(object):
         self.reset = reset
         self.bus = Bus(self.entity, name, self._signals, optional_signals=self._optional_signals, **kwargs)
 
+        self.log.info("AXI stream sink")
+        self.log.info("cocotbext-axi version %s", __version__)
+        self.log.info("Copyright (c) 2020 Alex Forencich")
+        self.log.info("https://github.com/alexforencich/cocotbext-axi")
+
         super().__init__(*args, **kwargs)
 
         self.active = False