Make wstrb optional
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@@ -60,6 +60,8 @@ class AxiLiteSlaveWrite(Reset):
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self.byte_lanes = self.width // self.byte_size
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self.strb_mask = 2**self.byte_lanes-1
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self.wstrb_present = hasattr(self.bus.w, "wstrb")
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self.log.info("AXI lite slave model configuration:")
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self.log.info(" Memory size: %d bytes", len(self.mem))
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self.log.info(" Address width: %d bits", self.address_width)
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@@ -74,7 +76,8 @@ class AxiLiteSlaveWrite(Reset):
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else:
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self.log.info(" %s: not present", sig)
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assert self.byte_lanes == len(self.w_channel.bus.wstrb)
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if self.wstrb_present:
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assert self.byte_lanes == len(self.w_channel.bus.wstrb)
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assert self.byte_lanes * self.byte_size == self.width
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self._process_write_cr = None
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@@ -109,7 +112,10 @@ class AxiLiteSlaveWrite(Reset):
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w = await self.w_channel.recv()
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data = int(w.wdata)
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strb = int(getattr(w, 'wstrb', self.strb_mask))
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if self.wstrb_present:
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strb = int(getattr(w, 'wstrb', self.strb_mask))
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else:
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strb = self.strb_mask
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# generate operation list
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offset = 0
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