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Update memory models to use SparseMemory

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2023-03-23 23:43:53 -07:00
parent 432bd81011
commit ad6012aea5
3 changed files with 11 additions and 14 deletions
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6
cocotbext/axi/axi_ram.py
View File

@@ -27,7 +27,7 @@ from .memory import Memory
class AxiRamWrite(AxiSlaveWrite, Memory):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=2**64, mem=None, **kwargs):
super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
async def _write(self, address, data):
@@ -35,7 +35,7 @@ class AxiRamWrite(AxiSlaveWrite, Memory):
class AxiRamRead(AxiSlaveRead, Memory):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=2**64, mem=None, **kwargs):
super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
async def _read(self, address, length):
@@ -43,7 +43,7 @@ class AxiRamRead(AxiSlaveRead, Memory):
class AxiRam(Memory):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=2**64, mem=None, **kwargs):
self.write_if = None
self.read_if = None

6
cocotbext/axi/axil_ram.py
View File

@@ -27,7 +27,7 @@ from .memory import Memory
class AxiLiteRamWrite(AxiLiteSlaveWrite, Memory):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=2**64, mem=None, **kwargs):
super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
async def _write(self, address, data):
@@ -35,7 +35,7 @@ class AxiLiteRamWrite(AxiLiteSlaveWrite, Memory):
class AxiLiteRamRead(AxiLiteSlaveRead, Memory):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=2**64, mem=None, **kwargs):
super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
async def _read(self, address, length):
@@ -43,7 +43,7 @@ class AxiLiteRamRead(AxiLiteSlaveRead, Memory):
class AxiLiteRam(Memory):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, **kwargs):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=2**64, mem=None, **kwargs):
self.write_if = None
self.read_if = None

13
cocotbext/axi/memory.py
View File

@@ -22,27 +22,24 @@ THE SOFTWARE.
"""
import mmap
from .sparse_memory import SparseMemory
from .utils import hexdump, hexdump_lines, hexdump_str
class Memory:
def __init__(self, size=1024, mem=None, **kwargs):
def __init__(self, size=2**64, mem=None, **kwargs):
if mem is not None:
self.mem = mem
else:
self.mem = mmap.mmap(-1, size)
self.mem = SparseMemory(size)
self.size = len(self.mem)
super().__init__(**kwargs)
def read(self, address, length):
self.mem.seek(address)
return self.mem.read(length)
return self.mem.read(address, length)
def write(self, address, data):
self.mem.seek(address)
self.mem.write(bytes(data))
self.mem.write(address, data)
def write_words(self, address, data, byteorder='little', ws=2):
words = data