Fix AxiStreamFrame default for self.byte_lanes from 1 to all.
If I connect a AXIS source to an AXIS sink, the #byte_lanes is incorrectly 1 rather than all lanes enabled. self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "sink"), dut.clk, dut.reset) Root cause is AxiStreamFrame assumes byte width 1 without TKEEP, but it should default to self.width // 8 because the AXIS specification mentions "when TKEEP is absent, TKEEP defaults to all bits HIGH" and "The width of the data payload is an integer number of bytes." Fix: https://github.com/alexforencich/cocotbext-axi/blob/master/cocotbext/axi/axis.py#L290 self.byte_lanes = 1 self.byte_lanes = self.width // 8 Relevant AXIS Specification: https://developer.arm.com/documentation/ihi0051/a/Default-Signaling-Requirements/Default-value-signaling/Optional-TKEEP-and-TSTRB?lang=en Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
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Alex Forencich
parent
035c1ba803
commit
afae9e69ff
@@ -287,7 +287,7 @@ class AxiStreamBase(Reset):
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self.queue_occupancy_frames = 0
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self.queue_occupancy_frames = 0
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self.width = len(self.bus.tdata)
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self.width = len(self.bus.tdata)
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self.byte_lanes = 1
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self.byte_lanes = self.width // 8
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if self._valid_init is not None and hasattr(self.bus, "tvalid"):
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if self._valid_init is not None and hasattr(self.bus, "tvalid"):
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self.bus.tvalid.setimmediatevalue(self._valid_init)
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self.bus.tvalid.setimmediatevalue(self._valid_init)
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