From bc7edec289de18132c7d002b93e435c5babacf95 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 12 Apr 2021 22:04:22 -0700 Subject: [PATCH] Make resp and prot signals optional --- cocotbext/axi/axi_channels.py | 16 ++++++++-------- cocotbext/axi/axi_master.py | 8 ++++++++ cocotbext/axi/axil_channels.py | 12 ++++++++---- cocotbext/axi/axil_master.py | 10 ++++++++++ 4 files changed, 34 insertions(+), 12 deletions(-) diff --git a/cocotbext/axi/axi_channels.py b/cocotbext/axi/axi_channels.py index fba2a49..0fbf367 100644 --- a/cocotbext/axi/axi_channels.py +++ b/cocotbext/axi/axi_channels.py @@ -26,8 +26,8 @@ from .stream import define_stream # Write address channel AxiAWBus, AxiAWTransaction, AxiAWSource, AxiAWSink, AxiAWMonitor = define_stream("AxiAW", - signals=["awid", "awaddr", "awlen", "awsize", "awburst", "awprot", "awvalid", "awready"], - optional_signals=["awlock", "awcache", "awqos", "awregion", "awuser"], + signals=["awid", "awaddr", "awlen", "awsize", "awburst", "awvalid", "awready"], + optional_signals=["awlock", "awcache", "awprot", "awqos", "awregion", "awuser"], signal_widths={"awlen": 8, "awsize": 3, "awburst": 2, "awlock": 1, "awcache": 4, "awprot": 3, "awqos": 4, "awregion": 4} ) @@ -41,23 +41,23 @@ AxiWBus, AxiWTransaction, AxiWSource, AxiWSink, AxiWMonitor = define_stream("Axi # Write response channel AxiBBus, AxiBTransaction, AxiBSource, AxiBSink, AxiBMonitor = define_stream("AxiB", - signals=["bid", "bresp", "bvalid", "bready"], - optional_signals=["buser"], + signals=["bid", "bvalid", "bready"], + optional_signals=["bresp", "buser"], signal_widths={"bresp": 2} ) # Read address channel AxiARBus, AxiARTransaction, AxiARSource, AxiARSink, AxiARMonitor = define_stream("AxiAR", - signals=["arid", "araddr", "arlen", "arsize", "arburst", "arprot", "arvalid", "arready"], - optional_signals=["arlock", "arcache", "arqos", "arregion", "aruser"], + signals=["arid", "araddr", "arlen", "arsize", "arburst", "arvalid", "arready"], + optional_signals=["arlock", "arcache", "arprot", "arqos", "arregion", "aruser"], signal_widths={"arlen": 8, "arsize": 3, "arburst": 2, "arlock": 1, "arcache": 4, "arprot": 3, "arqos": 4, "arregion": 4} ) # Read data channel AxiRBus, AxiRTransaction, AxiRSource, AxiRSink, AxiRMonitor = define_stream("AxiR", - signals=["rid", "rdata", "rresp", "rlast", "rvalid", "rready"], - optional_signals=["ruser"], + signals=["rid", "rdata", "rlast", "rvalid", "rready"], + optional_signals=["rresp", "ruser"], signal_widths={"rresp": 2, "rlast": 1} ) diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py index 07cd370..c91f733 100644 --- a/cocotbext/axi/axi_master.py +++ b/cocotbext/axi/axi_master.py @@ -177,6 +177,7 @@ class AxiMasterWrite(Reset): self.awlock_present = hasattr(self.bus.aw, "awlock") self.awcache_present = hasattr(self.bus.aw, "awcache") + self.awprot_present = hasattr(self.bus.aw, "awprot") self.awqos_present = hasattr(self.bus.aw, "awqos") self.awregion_present = hasattr(self.bus.aw, "awregion") self.awuser_present = hasattr(self.bus.aw, "awuser") @@ -240,6 +241,9 @@ class AxiMasterWrite(Reset): if not self.awcache_present and cache != 0b0011: raise ValueError("awcache sideband signal value specified, but signal is not connected") + if not self.awprot_present and prot != AxiProt.NONSECURE: + raise ValueError("awprot sideband signal value specified, but signal is not connected") + if not self.awqos_present and qos != 0: raise ValueError("awqos sideband signal value specified, but signal is not connected") @@ -558,6 +562,7 @@ class AxiMasterRead(Reset): self.arlock_present = hasattr(self.bus.ar, "arlock") self.arcache_present = hasattr(self.bus.ar, "arcache") + self.arprot_present = hasattr(self.bus.ar, "arprot") self.arqos_present = hasattr(self.bus.ar, "arqos") self.arregion_present = hasattr(self.bus.ar, "arregion") self.aruser_present = hasattr(self.bus.ar, "aruser") @@ -622,6 +627,9 @@ class AxiMasterRead(Reset): if not self.arcache_present and cache != 0b0011: raise ValueError("arcache sideband signal value specified, but signal is not connected") + if not self.arprot_present and prot != AxiProt.NONSECURE: + raise ValueError("arprot sideband signal value specified, but signal is not connected") + if not self.arqos_present and qos != 0: raise ValueError("arqos sideband signal value specified, but signal is not connected") diff --git a/cocotbext/axi/axil_channels.py b/cocotbext/axi/axil_channels.py index 8c38b72..35e121b 100644 --- a/cocotbext/axi/axil_channels.py +++ b/cocotbext/axi/axil_channels.py @@ -26,7 +26,8 @@ from .stream import define_stream # Write address channel AxiLiteAWBus, AxiLiteAWTransaction, AxiLiteAWSource, AxiLiteAWSink, AxiLiteAWMonitor = define_stream("AxiLiteAW", - signals=["awaddr", "awprot", "awvalid", "awready"], + signals=["awaddr", "awvalid", "awready"], + optional_signals=["awprot"], signal_widths={"awprot": 3} ) @@ -37,19 +38,22 @@ AxiLiteWBus, AxiLiteWTransaction, AxiLiteWSource, AxiLiteWSink, AxiLiteWMonitor # Write response channel AxiLiteBBus, AxiLiteBTransaction, AxiLiteBSource, AxiLiteBSink, AxiLiteBMonitor = define_stream("AxiLiteB", - signals=["bresp", "bvalid", "bready"], + signals=["bvalid", "bready"], + optional_signals=["bresp"], signal_widths={"bresp": 2} ) # Read address channel AxiLiteARBus, AxiLiteARTransaction, AxiLiteARSource, AxiLiteARSink, AxiLiteARMonitor = define_stream("AxiLiteAR", - signals=["araddr", "arprot", "arvalid", "arready"], + signals=["araddr", "arvalid", "arready"], + optional_signals=["arprot"], signal_widths={"arprot": 3} ) # Read data channel AxiLiteRBus, AxiLiteRTransaction, AxiLiteRSource, AxiLiteRSink, AxiLiteRMonitor = define_stream("AxiLiteR", - signals=["rdata", "rresp", "rvalid", "rready"], + signals=["rdata", "rvalid", "rready"], + optional_signals=["rresp"], signal_widths={"rresp": 2} ) diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py index f45adf3..03ba7ca 100644 --- a/cocotbext/axi/axil_master.py +++ b/cocotbext/axi/axil_master.py @@ -79,6 +79,8 @@ class AxiLiteMasterWrite(Reset): self.byte_lanes = self.width // self.byte_size self.strb_mask = 2**self.byte_lanes-1 + self.awprot_present = hasattr(self.bus.aw, "awprot") + self.log.info("AXI lite master configuration:") self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) self.log.info(" Byte size: %d bits", self.byte_size) @@ -107,6 +109,9 @@ class AxiLiteMasterWrite(Reset): if not isinstance(event, Event): raise ValueError("Expected event object") + if not self.awprot_present and prot != AxiProt.NONSECURE: + raise ValueError("awprot sideband signal value specified, but signal is not connected") + self.in_flight_operations += 1 self._idle.clear() @@ -311,6 +316,8 @@ class AxiLiteMasterRead(Reset): self.byte_size = 8 self.byte_lanes = self.width // self.byte_size + self.arprot_present = hasattr(self.bus.ar, "arprot") + self.log.info("AXI lite master configuration:") self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) self.log.info(" Byte size: %d bits", self.byte_size) @@ -338,6 +345,9 @@ class AxiLiteMasterRead(Reset): if not isinstance(event, Event): raise ValueError("Expected event object") + if not self.arprot_present and prot != AxiProt.NONSECURE: + raise ValueError("arprot sideband signal value specified, but signal is not connected") + self.in_flight_operations += 1 self._idle.clear()