diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py index c472377..c43d9a4 100644 --- a/cocotbext/axi/axi_master.py +++ b/cocotbext/axi/axi_master.py @@ -224,6 +224,8 @@ class AxiMasterWrite(Reset): self._idle = Event() self._idle.set() + self.address_width = len(self.aw_channel.bus.awaddr) + self.id_width = len(self.aw_channel.bus.awid) self.width = len(self.w_channel.bus.wdata) self.byte_size = 8 self.byte_lanes = self.width // self.byte_size @@ -242,8 +244,8 @@ class AxiMasterWrite(Reset): self.buser_present = hasattr(self.bus.b, "buser") self.log.info("AXI master configuration:") - self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) - self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid)) + self.log.info(" Address width: %d bits", self.address_width) + self.log.info(" ID width: %d bits", self.id_width) self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) self.log.info(" Max burst size: %d (%d bytes)", self.max_burst_size, 2**self.max_burst_size) @@ -611,6 +613,8 @@ class AxiMasterRead(Reset): self._idle = Event() self._idle.set() + self.address_width = len(self.ar_channel.bus.araddr) + self.id_width = len(self.ar_channel.bus.arid) self.width = len(self.r_channel.bus.rdata) self.byte_size = 8 self.byte_lanes = self.width // self.byte_size @@ -627,8 +631,8 @@ class AxiMasterRead(Reset): self.ruser_present = hasattr(self.bus.r, "ruser") self.log.info("AXI master configuration:") - self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) - self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid)) + self.log.info(" Address width: %d bits", self.address_width) + self.log.info(" ID width: %d bits", self.id_width) self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) self.log.info(" Max burst size: %d (%d bytes)", self.max_burst_size, 2**self.max_burst_size) diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py index 5f5a500..901c274 100644 --- a/cocotbext/axi/axi_ram.py +++ b/cocotbext/axi/axi_ram.py @@ -54,6 +54,8 @@ class AxiRamWrite(Memory, Reset): self.b_channel = AxiBSource(bus.b, clock, reset, reset_active_level) self.b_channel.queue_occupancy_limit = 2 + self.address_width = len(self.aw_channel.bus.awaddr) + self.id_width = len(self.aw_channel.bus.awid) self.width = len(self.w_channel.bus.wdata) self.byte_size = 8 self.byte_lanes = self.width // self.byte_size @@ -63,8 +65,8 @@ class AxiRamWrite(Memory, Reset): self.log.info("AXI RAM model configuration:") self.log.info(" Memory size: %d bytes", len(self.mem)) - self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) - self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid)) + self.log.info(" Address width: %d bits", self.address_width) + self.log.info(" ID width: %d bits", self.id_width) self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) @@ -192,6 +194,8 @@ class AxiRamRead(Memory, Reset): self.r_channel = AxiRSource(bus.r, clock, reset, reset_active_level) self.r_channel.queue_occupancy_limit = 2 + self.address_width = len(self.ar_channel.bus.araddr) + self.id_width = len(self.ar_channel.bus.arid) self.width = len(self.r_channel.bus.rdata) self.byte_size = 8 self.byte_lanes = self.width // self.byte_size @@ -200,8 +204,8 @@ class AxiRamRead(Memory, Reset): self.log.info("AXI RAM model configuration:") self.log.info(" Memory size: %d bytes", len(self.mem)) - self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) - self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid)) + self.log.info(" Address width: %d bits", self.address_width) + self.log.info(" ID width: %d bits", self.id_width) self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py index 0039d0e..a866647 100644 --- a/cocotbext/axi/axil_master.py +++ b/cocotbext/axi/axil_master.py @@ -111,6 +111,7 @@ class AxiLiteMasterWrite(Reset): self._idle = Event() self._idle.set() + self.address_width = len(self.aw_channel.bus.awaddr) self.width = len(self.w_channel.bus.wdata) self.byte_size = 8 self.byte_lanes = self.width // self.byte_size @@ -119,7 +120,7 @@ class AxiLiteMasterWrite(Reset): self.awprot_present = hasattr(self.bus.aw, "awprot") self.log.info("AXI lite master configuration:") - self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) + self.log.info(" Address width: %d bits", self.address_width) self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) @@ -350,6 +351,7 @@ class AxiLiteMasterRead(Reset): self._idle = Event() self._idle.set() + self.address_width = len(self.ar_channel.bus.araddr) self.width = len(self.r_channel.bus.rdata) self.byte_size = 8 self.byte_lanes = self.width // self.byte_size @@ -357,7 +359,7 @@ class AxiLiteMasterRead(Reset): self.arprot_present = hasattr(self.bus.ar, "arprot") self.log.info("AXI lite master configuration:") - self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) + self.log.info(" Address width: %d bits", self.address_width) self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py index 41d78fa..aa70479 100644 --- a/cocotbext/axi/axil_ram.py +++ b/cocotbext/axi/axil_ram.py @@ -54,6 +54,7 @@ class AxiLiteRamWrite(Memory, Reset): self.b_channel = AxiLiteBSource(bus.b, clock, reset, reset_active_level) self.b_channel.queue_occupancy_limit = 2 + self.address_width = len(self.aw_channel.bus.awaddr) self.width = len(self.w_channel.bus.wdata) self.byte_size = 8 self.byte_lanes = self.width // self.byte_size @@ -61,7 +62,7 @@ class AxiLiteRamWrite(Memory, Reset): self.log.info("AXI lite RAM model configuration:") self.log.info(" Memory size: %d bytes", len(self.mem)) - self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr)) + self.log.info(" Address width: %d bits", self.address_width) self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) @@ -148,13 +149,14 @@ class AxiLiteRamRead(Memory, Reset): self.r_channel = AxiLiteRSource(bus.r, clock, reset, reset_active_level) self.r_channel.queue_occupancy_limit = 2 + self.address_width = len(self.ar_channel.bus.araddr) self.width = len(self.r_channel.bus.rdata) self.byte_size = 8 self.byte_lanes = self.width // self.byte_size self.log.info("AXI lite RAM model configuration:") self.log.info(" Memory size: %d bytes", len(self.mem)) - self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr)) + self.log.info(" Address width: %d bits", self.address_width) self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)