Rework sim_build output directory, fix default makefile target

tests/axi/Makefile

@@ -42,8 +42,6 @@ export PARAM_BUSER_WIDTH ?= 1
 export PARAM_ARUSER_WIDTH ?= 1
 export PARAM_RUSER_WIDTH ?= 1
 
-SIM_BUILD ?= sim_build_$(MODULE)-$(PARAM_DATA_WIDTH)
-
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
 
@@ -79,6 +77,8 @@ else ifeq ($(SIM), verilator)
 	endif
 endif
 
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
 iverilog_dump.v:
 	echo 'module iverilog_dump();' > $@
 	echo 'initial begin' >> $@
@@ -88,9 +88,5 @@ iverilog_dump.v:
 	echo 'endmodule' >> $@
 
 clean::
-	@rm -rf sim_build_*
 	@rm -rf iverilog_dump.v
 	@rm -rf dump.fst $(TOPLEVEL).fst
-
-include $(shell cocotb-config --makefiles)/Makefile.sim
-

tests/axi/test_axi.py

@@ -338,8 +338,8 @@ def test_axi(request, data_width):
 
     extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
 
-    sim_build = os.path.join(tests_dir,
-        "sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
 
     cocotb_test.simulator.run(
         python_search=[tests_dir],