bslathi19/cocotbext-axi
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Rework sim_build output directory, fix default makefile target

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Alex Forencich
2020-12-29 14:25:44 -08:00
parent 1618220a30
commit c63d65bb87
6 changed files with 12 additions and 24 deletions
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8
tests/axi/Makefile
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@@ -42,8 +42,6 @@ export PARAM_BUSER_WIDTH ?= 1
export PARAM_ARUSER_WIDTH ?= 1
export PARAM_RUSER_WIDTH ?= 1
SIM_BUILD ?= sim_build_$(MODULE)-$(PARAM_DATA_WIDTH)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -79,6 +77,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -88,9 +88,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim