bslathi19/cocotbext-axi
1
0
Fork 0
Code Issues Actions Packages Projects Releases 5 Wiki Activity

Rework sim_build output directory, fix default makefile target

Browse Source
This commit is contained in:
Alex Forencich
2020-12-29 14:25:44 -08:00
parent 1618220a30
commit c63d65bb87
6 changed files with 12 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
tests/axis/Makefile
View File

@@ -38,8 +38,6 @@ export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_WIDTH ?= 1
SIM_BUILD ?= sim_build_$(MODULE)-$(PARAM_DATA_WIDTH)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -67,6 +65,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -76,9 +76,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim