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Rework sim_build output directory, fix default makefile target

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This commit is contained in:
Alex Forencich
2020-12-29 14:25:44 -08:00
parent 1618220a30
commit c63d65bb87
6 changed files with 12 additions and 24 deletions
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8
tests/axi/Makefile
View File

@@ -42,8 +42,6 @@ export PARAM_BUSER_WIDTH ?= 1
export PARAM_ARUSER_WIDTH ?= 1
export PARAM_RUSER_WIDTH ?= 1
SIM_BUILD ?= sim_build_$(MODULE)-$(PARAM_DATA_WIDTH)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -79,6 +77,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -88,9 +88,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

4
tests/axi/test_axi.py
View File

@@ -338,8 +338,8 @@ def test_axi(request, data_width):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],

8
tests/axil/Makefile
View File

@@ -36,8 +36,6 @@ export PARAM_DATA_WIDTH ?= 32
export PARAM_ADDR_WIDTH ?= 32
export PARAM_STRB_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
SIM_BUILD ?= sim_build_$(MODULE)-$(PARAM_DATA_WIDTH)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -61,6 +59,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -70,9 +70,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

4
tests/axil/test_axil.py
View File

@@ -316,8 +316,8 @@ def test_axil(request, data_width):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],

8
tests/axis/Makefile
View File

@@ -38,8 +38,6 @@ export PARAM_ID_WIDTH ?= 8
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_WIDTH ?= 1
SIM_BUILD ?= sim_build_$(MODULE)-$(PARAM_DATA_WIDTH)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -67,6 +65,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -76,9 +76,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

4
tests/axis/test_axis.py
View File

@@ -170,8 +170,8 @@ def test_axis(request, data_width):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],