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Rework testbench logging

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This commit is contained in:
Alex Forencich
2020-11-17 17:07:56 -08:00
parent f1648ccf78
commit ca57cdb198
3 changed files with 20 additions and 6 deletions
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10
tests/axi/test_axi.py
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@@ -31,6 +31,7 @@ import cocotb_test.simulator
import pytest
import cocotb
from cocotb.log import SimLog
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory
@@ -41,6 +42,9 @@ class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = SimLog(f"cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 2, units="ns").start())
self.axi_master = AxiMaster(dut, "axi", dut.clk, dut.rst)
@@ -93,7 +97,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None, si
for length in list(range(1,byte_width*2))+[1024]:
for offset in list(range(byte_width))+list(range(4096-byte_width,4096)):
print(f"length {length}, offset {offset}")
tb.log.info(f"length {length}, offset {offset}")
addr = offset+0x1000
test_data = bytearray([x%256 for x in range(length)])
@@ -101,7 +105,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None, si
await tb.axi_master.write(addr, test_data, size=size)
tb.axi_ram.hexdump((addr&0xfffffff0)-16, (((addr&0xf)+length-1)&0xfffffff0)+48)
tb.log.debug(tb.axi_ram.hexdump_str((addr&0xfffffff0)-16, (((addr&0xf)+length-1)&0xfffffff0)+48))
assert tb.axi_ram.read_mem(addr, length) == test_data
assert tb.axi_ram.read_mem(addr-1, 1) == b'\xaa'
@@ -127,7 +131,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None, siz
for length in list(range(1,byte_width*2))+[1024]:
for offset in list(range(byte_width))+list(range(4096-byte_width,4096)):
print(f"length {length}, offset {offset}")
tb.log.info(f"length {length}, offset {offset}")
addr = offset+0x1000
test_data = bytearray([x%256 for x in range(length)])