From cb4b0e1738ff5dbf898732f3385daf798a475a1f Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 16 Nov 2021 17:13:18 -0800 Subject: [PATCH] Wrap access on RAM size --- cocotbext/axi/axi_ram.py | 4 ++-- cocotbext/axi/axil_ram.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py index c636e73..c9f1c53 100644 --- a/cocotbext/axi/axi_ram.py +++ b/cocotbext/axi/axi_ram.py @@ -31,7 +31,7 @@ class AxiRamWrite(AxiSlaveWrite, Memory): super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs) async def _write(self, address, data): - self.write(address, data) + self.write(address % self.size, data) class AxiRamRead(AxiSlaveRead, Memory): @@ -39,7 +39,7 @@ class AxiRamRead(AxiSlaveRead, Memory): super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs) async def _read(self, address, length): - return self.read(address, length) + return self.read(address % self.size, length) class AxiRam(Memory): diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py index 2acfe17..ae653e4 100644 --- a/cocotbext/axi/axil_ram.py +++ b/cocotbext/axi/axil_ram.py @@ -31,7 +31,7 @@ class AxiLiteRamWrite(AxiLiteSlaveWrite, Memory): super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs) async def _write(self, address, data): - self.write(address, data) + self.write(address % self.size, data) class AxiLiteRamRead(AxiLiteSlaveRead, Memory): @@ -39,7 +39,7 @@ class AxiLiteRamRead(AxiLiteSlaveRead, Memory): super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs) async def _read(self, address, length): - return self.read(address, length) + return self.read(address % self.size, length) class AxiLiteRam(Memory):