From ce907ffbb919808fb446c6c90885afddb93479e7 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 12 Apr 2021 19:29:41 -0700 Subject: [PATCH] Print out signal summary --- cocotbext/axi/axi_master.py | 16 ++++++++++++++++ cocotbext/axi/axi_ram.py | 16 ++++++++++++++++ cocotbext/axi/axil_master.py | 16 ++++++++++++++++ cocotbext/axi/axil_ram.py | 16 ++++++++++++++++ cocotbext/axi/axis.py | 26 +++++++------------------- 5 files changed, 71 insertions(+), 19 deletions(-) diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py index 12026bb..5885403 100644 --- a/cocotbext/axi/axi_master.py +++ b/cocotbext/axi/axi_master.py @@ -184,6 +184,14 @@ class AxiMasterWrite(Reset): self.log.info(" Max burst length: %d cycles (%d bytes)", self.max_burst_len, self.max_burst_len*self.byte_lanes) + self.log.info("AXI master signals:") + for bus in (self.bus.aw, self.bus.w, self.bus.b): + for sig in sorted(list(set().union(bus._signals, bus._optional_signals))): + if hasattr(bus, sig): + self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig))) + else: + self.log.info(" %s: not present", sig) + assert self.byte_lanes == len(self.w_channel.bus.wstrb) assert self.byte_lanes * self.byte_size == self.width @@ -528,6 +536,14 @@ class AxiMasterRead(Reset): self.log.info(" Max burst length: %d cycles (%d bytes)", self.max_burst_len, self.max_burst_len*self.byte_lanes) + self.log.info("AXI master signals:") + for bus in (self.bus.ar, self.bus.r): + for sig in sorted(list(set().union(bus._signals, bus._optional_signals))): + if hasattr(bus, sig): + self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig))) + else: + self.log.info(" %s: not present", sig) + assert self.byte_lanes * self.byte_size == self.width assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid) diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py index df6d486..f70aba6 100644 --- a/cocotbext/axi/axi_ram.py +++ b/cocotbext/axi/axi_ram.py @@ -66,6 +66,14 @@ class AxiRamWrite(Memory, Reset): self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) + self.log.info("AXI RAM model signals:") + for bus in (self.bus.aw, self.bus.w, self.bus.b): + for sig in sorted(list(set().union(bus._signals, bus._optional_signals))): + if hasattr(bus, sig): + self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig))) + else: + self.log.info(" %s: not present", sig) + assert self.byte_lanes == len(self.w_channel.bus.wstrb) assert self.byte_lanes * self.byte_size == self.width @@ -192,6 +200,14 @@ class AxiRamRead(Memory, Reset): self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) + self.log.info("AXI RAM model signals:") + for bus in (self.bus.ar, self.bus.r): + for sig in sorted(list(set().union(bus._signals, bus._optional_signals))): + if hasattr(bus, sig): + self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig))) + else: + self.log.info(" %s: not present", sig) + assert self.byte_lanes * self.byte_size == self.width assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid) diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py index f77678b..f45adf3 100644 --- a/cocotbext/axi/axil_master.py +++ b/cocotbext/axi/axil_master.py @@ -84,6 +84,14 @@ class AxiLiteMasterWrite(Reset): self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) + self.log.info("AXI lite master signals:") + for bus in (self.bus.aw, self.bus.w, self.bus.b): + for sig in sorted(list(set().union(bus._signals, bus._optional_signals))): + if hasattr(bus, sig): + self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig))) + else: + self.log.info(" %s: not present", sig) + assert self.byte_lanes == len(self.w_channel.bus.wstrb) assert self.byte_lanes * self.byte_size == self.width @@ -308,6 +316,14 @@ class AxiLiteMasterRead(Reset): self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) + self.log.info("AXI lite master signals:") + for bus in (self.bus.ar, self.bus.r): + for sig in sorted(list(set().union(bus._signals, bus._optional_signals))): + if hasattr(bus, sig): + self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig))) + else: + self.log.info(" %s: not present", sig) + assert self.byte_lanes * self.byte_size == self.width self._process_read_cr = None diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py index 29f3fcf..2977fb1 100644 --- a/cocotbext/axi/axil_ram.py +++ b/cocotbext/axi/axil_ram.py @@ -65,6 +65,14 @@ class AxiLiteRamWrite(Memory, Reset): self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) + self.log.info("AXI lite RAM model signals:") + for bus in (self.bus.aw, self.bus.w, self.bus.b): + for sig in sorted(list(set().union(bus._signals, bus._optional_signals))): + if hasattr(bus, sig): + self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig))) + else: + self.log.info(" %s: not present", sig) + assert self.byte_lanes == len(self.w_channel.bus.wstrb) assert self.byte_lanes * self.byte_size == self.width @@ -149,6 +157,14 @@ class AxiLiteRamRead(Memory, Reset): self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) + self.log.info("AXI lite RAM model signals:") + for bus in (self.bus.ar, self.bus.r): + for sig in sorted(list(set().union(bus._signals, bus._optional_signals))): + if hasattr(bus, sig): + self.log.info(" %s width: %d bits", sig, len(getattr(bus, sig))) + else: + self.log.info(" %s: not present", sig) + assert self.byte_lanes * self.byte_size == self.width self._process_read_cr = None diff --git a/cocotbext/axi/axis.py b/cocotbext/axi/axis.py index 71694a3..c3a598b 100644 --- a/cocotbext/axi/axis.py +++ b/cocotbext/axi/axis.py @@ -319,25 +319,13 @@ class AxiStreamBase(Reset): self.log.info("AXI stream %s configuration:", self._type) self.log.info(" Byte size: %d bits", self.byte_size) self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) - self.log.info(" tvalid: %s", "present" if hasattr(self.bus, "tvalid") else "not present") - self.log.info(" tready: %s", "present" if hasattr(self.bus, "tready") else "not present") - self.log.info(" tlast: %s", "present" if hasattr(self.bus, "tlast") else "not present") - if hasattr(self.bus, "tkeep"): - self.log.info(" tkeep width: %d bits", len(self.bus.tkeep)) - else: - self.log.info(" tkeep: not present") - if hasattr(self.bus, "tid"): - self.log.info(" tid width: %d bits", len(self.bus.tid)) - else: - self.log.info(" tid: not present") - if hasattr(self.bus, "tdest"): - self.log.info(" tdest width: %d bits", len(self.bus.tdest)) - else: - self.log.info(" tdest: not present") - if hasattr(self.bus, "tuser"): - self.log.info(" tuser width: %d bits", len(self.bus.tuser)) - else: - self.log.info(" tuser: not present") + + self.log.info("AXI stream %s signals:", self._type) + for sig in sorted(list(set().union(self.bus._signals, self.bus._optional_signals))): + if hasattr(self.bus, sig): + self.log.info(" %s width: %d bits", sig, len(getattr(self.bus, sig))) + else: + self.log.info(" %s: not present", sig) if self.byte_lanes * self.byte_size != self.width: raise ValueError(f"Bus does not evenly divide into byte lanes "