From cf67943bf8fd24ce4491319d7c904bcea61a34d8 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 1 Dec 2020 22:51:28 -0800 Subject: [PATCH] Test word access --- tests/axi/test_axi.py | 103 ++++++++++++++++++++++++++++++++++++++++ tests/axil/test_axil.py | 103 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 206 insertions(+) diff --git a/tests/axi/test_axi.py b/tests/axi/test_axi.py index b23d160..7c69818 100644 --- a/tests/axi/test_axi.py +++ b/tests/axi/test_axi.py @@ -147,6 +147,104 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None, siz await RisingEdge(dut.clk) +async def run_test_write_words(dut): + + tb = TB(dut) + + byte_width = tb.axi_master.write_if.byte_width + + await tb.cycle_reset() + + for length in list(range(1, 4)): + for offset in list(range(byte_width)): + tb.log.info(f"length {length}, offset {offset}") + addr = offset+0x1000 + + test_data = bytearray([x % 256 for x in range(length)]) + await tb.axi_master.write(addr, test_data) + assert tb.axi_ram.read(addr, length) == test_data + + test_data = [x * 0x1001 for x in range(length)] + await tb.axi_master.write_words(addr, test_data) + assert tb.axi_ram.read_words(addr, length) == test_data + + test_data = [x * 0x10200201 for x in range(length)] + await tb.axi_master.write_dwords(addr, test_data) + assert tb.axi_ram.read_dwords(addr, length) == test_data + + test_data = [x * 0x1020304004030201 for x in range(length)] + await tb.axi_master.write_qwords(addr, test_data) + assert tb.axi_ram.read_qwords(addr, length) == test_data + + test_data = 0x01*length + await tb.axi_master.write_byte(addr, test_data) + assert tb.axi_ram.read_byte(addr) == test_data + + test_data = 0x1001*length + await tb.axi_master.write_word(addr, test_data) + assert tb.axi_ram.read_word(addr) == test_data + + test_data = 0x10200201*length + await tb.axi_master.write_dword(addr, test_data) + assert tb.axi_ram.read_dword(addr) == test_data + + test_data = 0x1020304004030201*length + await tb.axi_master.write_qword(addr, test_data) + assert tb.axi_ram.read_qword(addr) == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_read_words(dut): + + tb = TB(dut) + + byte_width = tb.axi_master.write_if.byte_width + + await tb.cycle_reset() + + for length in list(range(1, 4)): + for offset in list(range(byte_width)): + tb.log.info(f"length {length}, offset {offset}") + addr = offset+0x1000 + + test_data = bytearray([x % 256 for x in range(length)]) + tb.axi_ram.write(addr, test_data) + assert (await tb.axi_master.read(addr, length)).data == test_data + + test_data = [x * 0x1001 for x in range(length)] + tb.axi_ram.write_words(addr, test_data) + assert await tb.axi_master.read_words(addr, length) == test_data + + test_data = [x * 0x10200201 for x in range(length)] + tb.axi_ram.write_dwords(addr, test_data) + assert await tb.axi_master.read_dwords(addr, length) == test_data + + test_data = [x * 0x1020304004030201 for x in range(length)] + tb.axi_ram.write_qwords(addr, test_data) + assert await tb.axi_master.read_qwords(addr, length) == test_data + + test_data = 0x01*length + tb.axi_ram.write_byte(addr, test_data) + assert await tb.axi_master.read_byte(addr) == test_data + + test_data = 0x1001*length + tb.axi_ram.write_word(addr, test_data) + assert await tb.axi_master.read_word(addr) == test_data + + test_data = 0x10200201*length + tb.axi_ram.write_dword(addr, test_data) + assert await tb.axi_master.read_dword(addr) == test_data + + test_data = 0x1020304004030201*length + tb.axi_ram.write_qword(addr, test_data) + assert await tb.axi_master.read_qword(addr) == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -201,6 +299,11 @@ if cocotb.SIM_NAME: factory.add_option("size", [None]+list(range(max_burst_size))) factory.generate_tests() + for test in [run_test_write_words, run_test_read_words]: + + factory = TestFactory(test) + factory.generate_tests() + factory = TestFactory(run_stress_test) factory.generate_tests() diff --git a/tests/axil/test_axil.py b/tests/axil/test_axil.py index e44377b..fa4fde9 100644 --- a/tests/axil/test_axil.py +++ b/tests/axil/test_axil.py @@ -136,6 +136,104 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse await RisingEdge(dut.clk) +async def run_test_write_words(dut): + + tb = TB(dut) + + byte_width = tb.axil_master.write_if.byte_width + + await tb.cycle_reset() + + for length in list(range(1, 4)): + for offset in list(range(byte_width)): + tb.log.info(f"length {length}, offset {offset}") + addr = offset+0x1000 + + test_data = bytearray([x % 256 for x in range(length)]) + await tb.axil_master.write(addr, test_data) + assert tb.axil_ram.read(addr, length) == test_data + + test_data = [x * 0x1001 for x in range(length)] + await tb.axil_master.write_words(addr, test_data) + assert tb.axil_ram.read_words(addr, length) == test_data + + test_data = [x * 0x10200201 for x in range(length)] + await tb.axil_master.write_dwords(addr, test_data) + assert tb.axil_ram.read_dwords(addr, length) == test_data + + test_data = [x * 0x1020304004030201 for x in range(length)] + await tb.axil_master.write_qwords(addr, test_data) + assert tb.axil_ram.read_qwords(addr, length) == test_data + + test_data = 0x01*length + await tb.axil_master.write_byte(addr, test_data) + assert tb.axil_ram.read_byte(addr) == test_data + + test_data = 0x1001*length + await tb.axil_master.write_word(addr, test_data) + assert tb.axil_ram.read_word(addr) == test_data + + test_data = 0x10200201*length + await tb.axil_master.write_dword(addr, test_data) + assert tb.axil_ram.read_dword(addr) == test_data + + test_data = 0x1020304004030201*length + await tb.axil_master.write_qword(addr, test_data) + assert tb.axil_ram.read_qword(addr) == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_read_words(dut): + + tb = TB(dut) + + byte_width = tb.axil_master.write_if.byte_width + + await tb.cycle_reset() + + for length in list(range(1, 4)): + for offset in list(range(byte_width)): + tb.log.info(f"length {length}, offset {offset}") + addr = offset+0x1000 + + test_data = bytearray([x % 256 for x in range(length)]) + tb.axil_ram.write(addr, test_data) + assert (await tb.axil_master.read(addr, length)).data == test_data + + test_data = [x * 0x1001 for x in range(length)] + tb.axil_ram.write_words(addr, test_data) + assert await tb.axil_master.read_words(addr, length) == test_data + + test_data = [x * 0x10200201 for x in range(length)] + tb.axil_ram.write_dwords(addr, test_data) + assert await tb.axil_master.read_dwords(addr, length) == test_data + + test_data = [x * 0x1020304004030201 for x in range(length)] + tb.axil_ram.write_qwords(addr, test_data) + assert await tb.axil_master.read_qwords(addr, length) == test_data + + test_data = 0x01*length + tb.axil_ram.write_byte(addr, test_data) + assert await tb.axil_master.read_byte(addr) == test_data + + test_data = 0x1001*length + tb.axil_ram.write_word(addr, test_data) + assert await tb.axil_master.read_word(addr) == test_data + + test_data = 0x10200201*length + tb.axil_ram.write_dword(addr, test_data) + assert await tb.axil_master.read_dword(addr) == test_data + + test_data = 0x1020304004030201*length + tb.axil_ram.write_qword(addr, test_data) + assert await tb.axil_master.read_qword(addr) == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -185,6 +283,11 @@ if cocotb.SIM_NAME: factory.add_option("backpressure_inserter", [None, cycle_pause]) factory.generate_tests() + for test in [run_test_write_words, run_test_read_words]: + + factory = TestFactory(test) + factory.generate_tests() + factory = TestFactory(run_stress_test) factory.generate_tests()